Lines Matching +full:0 +full:x27200
20 qcom,msm-id = <458 0x10000>, <483 0x10000>, <509 0x10000>;
25 reg = <0 0>;
33 #clock-cells = <0>;
40 #clock-cells = <0>;
46 #clock-cells = <0>;
52 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x0>;
115 reg = <0x8fcad000 0x40000>;
120 reg = <0x8fcfd000 0x1000>;
125 reg = <0x8fd00000 0x80000>;
130 reg = <0x8fd80000 0x80000>;
135 reg = <0x8fe00000 0x20000>;
140 reg = <0x8fe20000 0xc0000>;
147 reg = <0x8fee0000 0x20000>;
153 reg = <0x8ff00000 0x100000>;
158 reg = <0x90000000 0x500000>;
163 reg = <0x15800000 0x800000>;
172 qcom,local-pid = <0>;
206 reg = <0x00100000 0x001f7400>;
216 reg = <0x00831000 0x200>;
226 reg = <0xff4000 0x120>;
227 #phy-cells = <0>;
236 reg = <0x00ff6000 0x1c8>;
253 reg = <0x00ff6e00 0x160>,
254 <0x00ff7000 0x1ec>,
255 <0x00ff6200 0x1e00>;
256 #phy-cells = <0>;
257 #clock-cells = <0>;
266 reg = <0x01620000 0x31200>;
273 reg = <0x01b04000 0x1c000>;
278 qcom,ee = <0>;
285 reg = <0x01b30000 0x10000>;
287 #size-cells = <0>;
292 dmas = <&qpic_bam 0>,
301 reg = <0x01c00000 0x3000>,
302 <0x40000000 0xf1d>,
303 <0x40000f20 0xa8>,
304 <0x40001000 0x1000>,
305 <0x40200000 0x100000>,
306 <0x01c03000 0x3000>;
314 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
351 reg = <0x01c06000 0x2000>;
372 #clock-cells = <0>;
375 #phy-cells = <0>;
382 reg = <0x01f40000 0x40000>;
388 reg = <0x01fc0000 0x1000>;
394 reg = <0x03f40000 0x10000>,
395 <0x03f50000 0x5000>,
396 <0x03e04000 0xfc000>;
403 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
410 iommus = <&apps_smmu 0x5e0 0x0>,
411 <&apps_smmu 0x5e2 0x0>;
421 qcom,smem-states = <&ipa_smp2p_out 0>,
431 reg = <0x04080000 0x4040>;
434 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
449 qcom,smem-states = <&modem_smp2p_out 0>;
464 reg = <0x08804000 0x1000>;
477 reg = <0x09680000 0x27200>;
484 reg = <0x0a6f8800 0x400>;
518 reg = <0x0a600000 0xcd00>;
520 iommus = <&apps_smmu 0x1a0 0x0>;
530 reg = <0x0c264000 0x1000>;
535 reg = <0xc440000 0xd00>,
536 <0xc600000 0x2000000>,
537 <0xe600000 0x100000>,
538 <0xe700000 0xa0000>,
539 <0xc40a000 0x26000>;
546 #size-cells = <0>;
547 cell-index = <0>;
548 qcom,channel = <0>;
549 qcom,ee = <0>;
554 reg = <0xf100000 0x300000>;
558 gpio-ranges = <&tlmm 0 0 109>;
566 reg = <0xb210000 0x10000>;
567 qcom,pdc-ranges = <0 147 52>, <52 266 32>;
575 reg = <0x1468f000 0x1000>;
576 ranges = <0x0 0x1468f000 0x1000>;
582 reg = <0x94c 0xc8>;
588 reg = <0x15000000 0x40000>;
631 reg = <0x17800000 0x1000>,
632 <0x17802000 0x1000>;
637 reg = <0x17808000 0x1000>;
640 #clock-cells = <0>;
645 reg = <0x17810000 0x2000>;
649 #clock-cells = <0>;
654 reg = <0x17817000 0x1000>;
663 reg = <0x17820000 0x1000>;
667 frame-number = <0>;
668 interrupts = <GIC_SPI 7 0x4>,
669 <GIC_SPI 6 0x4>;
670 reg = <0x17821000 0x1000>,
671 <0x17822000 0x1000>;
676 interrupts = <GIC_SPI 8 0x4>;
677 reg = <0x17823000 0x1000>;
683 interrupts = <GIC_SPI 9 0x4>;
684 reg = <0x17824000 0x1000>;
690 interrupts = <GIC_SPI 10 0x4>;
691 reg = <0x17825000 0x1000>;
697 interrupts = <GIC_SPI 11 0x4>;
698 reg = <0x17826000 0x1000>;
704 interrupts = <GIC_SPI 12 0x4>;
705 reg = <0x17827000 0x1000>;
711 interrupts = <GIC_SPI 13 0x4>;
712 reg = <0x17828000 0x1000>;
718 interrupts = <GIC_SPI 14 0x4>;
719 reg = <0x17829000 0x1000>;
727 reg = <0x17830000 0x10000>,
728 <0x17840000 0x10000>;
729 reg-names = "drv-0", "drv-1";
732 qcom,tcs-offset = <0xd00>;
805 interrupts = <1 13 0xf08>,
806 <1 12 0xf08>,
807 <1 10 0xf08>,
808 <1 11 0xf08>;