Lines Matching +full:bcm +full:- +full:voter +full:- +full:names
1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interconnect/qcom,sdx55.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
21 interrupt-parent = <&intc>;
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <38400000>;
33 clock-output-names = "xo_board";
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <32000>;
42 nand_clk_dummy: nand-clk-dummy {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <32000>;
50 #address-cells = <1>;
51 #size-cells = <0>;
55 compatible = "arm,cortex-a7";
57 enable-method = "psci";
59 power-domains = <&rpmhpd SDX55_CX>;
60 power-domain-names = "rpmhpd";
61 operating-points-v2 = <&cpu_opp_table>;
67 compatible = "qcom,scm-sdx55", "qcom,scm";
71 cpu_opp_table: opp-table-cpu {
72 compatible = "operating-points-v2";
73 opp-shared;
75 opp-345600000 {
76 opp-hz = /bits/ 64 <345600000>;
77 required-opps = <&rpmhpd_opp_low_svs>;
80 opp-576000000 {
81 opp-hz = /bits/ 64 <576000000>;
82 required-opps = <&rpmhpd_opp_svs>;
85 opp-1094400000 {
86 opp-hz = /bits/ 64 <1094400000>;
87 required-opps = <&rpmhpd_opp_nom>;
90 opp-1555200000 {
91 opp-hz = /bits/ 64 <1555200000>;
92 required-opps = <&rpmhpd_opp_turbo>;
97 compatible = "arm,psci-1.0";
101 reserved-memory {
102 #address-cells = <1>;
103 #size-cells = <1>;
107 no-map;
112 no-map;
117 no-map;
122 no-map;
127 no-map;
132 compatible = "qcom,cmd-db";
134 no-map;
138 no-map;
143 no-map;
148 no-map;
155 memory-region = <&smem_mem>;
159 smp2p-mpss {
164 qcom,local-pid = <0>;
165 qcom,remote-pid = <1>;
167 modem_smp2p_out: master-kernel {
168 qcom,entry-name = "master-kernel";
169 #qcom,smem-state-cells = <1>;
172 modem_smp2p_in: slave-kernel {
173 qcom,entry-name = "slave-kernel";
174 interrupt-controller;
175 #interrupt-cells = <2>;
178 ipa_smp2p_out: ipa-ap-to-modem {
179 qcom,entry-name = "ipa";
180 #qcom,smem-state-cells = <1>;
183 ipa_smp2p_in: ipa-modem-to-ap {
184 qcom,entry-name = "ipa";
185 interrupt-controller;
186 #interrupt-cells = <2>;
191 #address-cells = <1>;
192 #size-cells = <1>;
194 compatible = "simple-bus";
196 gcc: clock-controller@100000 {
197 compatible = "qcom,gcc-sdx55";
199 #clock-cells = <1>;
200 #reset-cells = <1>;
201 #power-domain-cells = <1>;
202 clock-names = "bi_tcxo", "sleep_clk";
207 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
212 clock-names = "core", "iface";
217 compatible = "qcom,sdx55-usb-hs-phy",
218 "qcom,usb-snps-hs-7nm-phy";
221 #phy-cells = <0>;
224 clock-names = "ref";
230 compatible = "qcom,sdx55-qmp-usb3-uni-phy";
233 #address-cells = <1>;
234 #size-cells = <1>;
240 clock-names = "aux", "cfg_ahb", "ref";
244 reset-names = "phy", "common";
250 #phy-cells = <0>;
251 #clock-cells = <0>;
253 clock-names = "pipe0";
254 clock-output-names = "usb3_uni_phy_pipe_clk_src";
259 compatible = "qcom,sdx55-mc-virt";
261 #interconnect-cells = <1>;
262 qcom,bcm-voters = <&apps_bcm_voter>;
266 compatible = "qcom,sdx55-mem-noc";
268 #interconnect-cells = <1>;
269 qcom,bcm-voters = <&apps_bcm_voter>;
273 compatible = "qcom,sdx55-system-noc";
275 #interconnect-cells = <1>;
276 qcom,bcm-voters = <&apps_bcm_voter>;
279 qpic_bam: dma-controller@1b04000 {
280 compatible = "qcom,bam-v1.7.0";
284 clock-names = "bam_clk";
285 #dma-cells = <1>;
287 qcom,controlled-remotely;
291 qpic_nand: nand-controller@1b30000 {
292 compatible = "qcom,sdx55-nand";
294 #address-cells = <1>;
295 #size-cells = <0>;
298 clock-names = "core", "aon";
303 dma-names = "tx", "rx", "cmd";
308 compatible = "qcom,pcie-sdx55";
314 reg-names = "parf",
320 linux,pci-domain = <0>;
321 bus-range = <0x00 0xff>;
322 num-lanes = <1>;
324 #address-cells = <3>;
325 #size-cells = <2>;
338 interrupt-names = "msi",
346 #interrupt-cells = <1>;
347 interrupt-map-mask = <0 0 0 0x7>;
348 interrupt-map = <0 0 0 1 &intc 0 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
360 clock-names = "pipe",
368 assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
369 assigned-clock-rates = <19200000>;
371 iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
378 reset-names = "pci";
380 power-domains = <&gcc PCIE_GDSC>;
383 phy-names = "pciephy";
388 pcie_ep: pcie-ep@1c00000 {
389 compatible = "qcom,sdx55-pcie-ep";
396 reg-names = "parf",
403 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
412 clock-names = "aux",
422 interrupt-names = "global",
426 interconnect-names = "pcie-mem";
429 reset-names = "core";
430 power-domains = <&gcc PCIE_GDSC>;
432 phy-names = "pciephy";
433 max-link-speed = <3>;
434 num-lanes = <2>;
440 compatible = "qcom,sdx55-qmp-pcie-phy";
442 #address-cells = <1>;
443 #size-cells = <1>;
449 clock-names = "aux",
455 reset-names = "phy";
457 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
458 assigned-clock-rates = <100000000>;
470 clock-names = "pipe0";
472 #phy-cells = <0>;
473 clock-output-names = "pcie_pipe_clk";
478 compatible = "qcom,sdx55-ipa";
485 reg-names = "ipa-reg",
486 "ipa-shared",
489 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
493 interrupt-names = "ipa",
495 "ipa-clock-query",
496 "ipa-setup-ready";
499 clock-names = "core";
504 interconnect-names = "memory",
508 qcom,smem-states = <&ipa_smp2p_out 0>,
510 qcom,smem-state-names = "ipa-clock-enabled-valid",
511 "ipa-clock-enabled";
517 compatible = "qcom,tcsr-mutex";
519 #hwlock-cells = <1>;
523 compatible = "qcom,sdx55-tcsr", "syscon";
528 compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
532 interrupt-names = "hc_irq", "pwr_irq";
535 clock-names = "iface", "core";
540 compatible = "qcom,sdx55-mpss-pas";
543 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
549 interrupt-names = "wdog", "fatal", "ready", "handover",
550 "stop-ack", "shutdown-ack";
553 clock-names = "xo";
555 power-domains = <&rpmhpd SDX55_CX>,
557 power-domain-names = "cx", "mss";
559 qcom,smem-states = <&modem_smp2p_out 0>;
560 qcom,smem-state-names = "stop";
564 glink-edge {
567 qcom,remote-pid = <1>;
573 compatible = "qcom,sdx55-dwc3", "qcom,dwc3";
576 #address-cells = <1>;
577 #size-cells = <1>;
585 clock-names = "cfg_noc",
591 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
593 assigned-clock-rates = <19200000>, <200000000>;
595 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
599 interrupt-names = "hs_phy_irq", "ss_phy_irq",
602 power-domains = <&gcc USB30_GDSC>;
614 phy-names = "usb2-phy", "usb3-phy";
618 pdc: interrupt-controller@b210000 {
619 compatible = "qcom,sdx55-pdc", "qcom,pdc";
621 qcom,pdc-ranges = <0 179 52>;
622 #interrupt-cells = <2>;
623 interrupt-parent = <&intc>;
624 interrupt-controller;
633 compatible = "qcom,spmi-pmic-arb";
639 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
640 interrupt-names = "periph_irq";
644 #address-cells = <2>;
645 #size-cells = <0>;
646 interrupt-controller;
647 #interrupt-cells = <4>;
648 cell-index = <0>;
652 compatible = "qcom,sdx55-pinctrl";
655 gpio-controller;
656 #gpio-cells = <2>;
657 interrupt-controller;
658 #interrupt-cells = <2>;
659 gpio-ranges = <&tlmm 0 0 108>;
663 compatible = "qcom,sdx55-imem", "syscon", "simple-mfd";
666 #address-cells = <1>;
667 #size-cells = <1>;
671 pil-reloc@94c {
672 compatible = "qcom,pil-reloc-info";
678 compatible = "qcom,sdx55-smmu-500", "qcom,smmu-500", "arm,mmu-500";
680 #iommu-cells = <2>;
681 #global-interrupts = <1>;
701 intc: interrupt-controller@17800000 {
702 compatible = "qcom,msm-qgic2";
703 interrupt-controller;
704 interrupt-parent = <&intc>;
705 #interrupt-cells = <3>;
711 compatible = "qcom,sdx55-a7pll";
714 clock-names = "bi_tcxo";
715 #clock-cells = <0>;
719 compatible = "qcom,sdx55-apcs-gcc", "syscon";
721 #mbox-cells = <1>;
723 clock-names = "ref", "pll", "aux";
724 #clock-cells = <0>;
728 compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";
734 #address-cells = <1>;
735 #size-cells = <1>;
737 compatible = "arm,armv7-timer-mem";
739 clock-frequency = <19200000>;
742 frame-number = <0>;
750 frame-number = <1>;
757 frame-number = <2>;
764 frame-number = <3>;
771 frame-number = <4>;
778 frame-number = <5>;
785 frame-number = <6>;
792 frame-number = <7>;
800 compatible = "qcom,rpmh-rsc";
802 reg-names = "drv-0", "drv-1";
805 qcom,tcs-offset = <0xd00>;
806 qcom,drv-id = <1>;
807 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>,
810 rpmhcc: clock-controller {
811 compatible = "qcom,sdx55-rpmh-clk";
812 #clock-cells = <1>;
813 clock-names = "xo";
817 rpmhpd: power-controller {
818 compatible = "qcom,sdx55-rpmhpd";
819 #power-domain-cells = <1>;
820 operating-points-v2 = <&rpmhpd_opp_table>;
822 rpmhpd_opp_table: opp-table {
823 compatible = "operating-points-v2";
826 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
830 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
834 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
838 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
842 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
846 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
850 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
854 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
858 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
862 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
867 apps_bcm_voter: bcm-voter {
868 compatible = "qcom,bcm-voter";
874 compatible = "arm,armv7-timer";
879 clock-frequency = <19200000>;