Lines Matching +full:0 +full:xfdb00000
20 #clock-cells = <0>;
26 #clock-cells = <0>;
33 #size-cells = <0>;
34 interrupts = <GIC_PPI 9 0xf04>;
36 CPU0: cpu@0 {
40 reg = <0>;
108 reg = <0x0 0x0>;
113 interrupts = <GIC_PPI 7 0xf04>;
121 qcom,ipc = <&apcs 8 0>;
144 reg = <0x08000000 0x5100000>;
149 reg = <0x0d100000 0x100000>;
154 reg = <0x0d200000 0xa00000>;
159 reg = <0x0dc00000 0x1900000>;
164 reg = <0x0f500000 0x500000>;
169 reg = <0xfa00000 0x200000>;
174 reg = <0x0fc00000 0x160000>;
179 reg = <0x0fd60000 0x20000>;
185 reg = <0x0fd80000 0x180000>;
210 qcom,local-pid = <0>;
235 qcom,local-pid = <0>;
260 qcom,local-pid = <0>;
281 #size-cells = <0>;
287 apps_smsm: apps@0 {
288 reg = <0>;
328 reg = <0xf9000000 0x1000>,
329 <0xf9002000 0x1000>;
334 reg = <0xf9011000 0x1000>;
342 reg = <0xf9020000 0x1000>;
346 frame-number = <0>;
349 reg = <0xf9021000 0x1000>,
350 <0xf9022000 0x1000>;
356 reg = <0xf9023000 0x1000>;
363 reg = <0xf9024000 0x1000>;
370 reg = <0xf9025000 0x1000>;
377 reg = <0xf9026000 0x1000>;
384 reg = <0xf9027000 0x1000>;
391 reg = <0xf9028000 0x1000>;
398 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
403 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
408 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
413 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
418 reg = <0xf9012000 0x1000>;
424 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
429 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
434 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
439 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
444 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
461 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
473 #size-cells = <0>;
480 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
492 #size-cells = <0>;
499 reg = <0xf991d000 0x1000>;
508 reg = <0xf991e000 0x1000>;
513 pinctrl-0 = <&blsp1_uart2_default>;
520 reg = <0xf9923000 0x1000>;
521 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
525 pinctrl-0 = <&blsp1_i2c1_default>;
528 #size-cells = <0>;
534 reg = <0xf9924000 0x1000>;
539 pinctrl-0 = <&blsp1_i2c2_default>;
542 #size-cells = <0>;
548 reg = <0xf9925000 0x1000>;
549 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
553 pinctrl-0 = <&blsp1_i2c3_default>;
556 #size-cells = <0>;
562 reg = <0xf9928000 0x1000>;
567 pinctrl-0 = <&blsp1_i2c6_default>;
570 #size-cells = <0>;
575 reg = <0xf9944000 0x19000>;
580 qcom,ee = <0>;
585 reg = <0xf995d000 0x1000>;
590 pinctrl-0 = <&blsp2_uart1_default>;
597 reg = <0xf995e000 0x1000>;
606 reg = <0xf9960000 0x1000>;
611 pinctrl-0 = <&blsp2_uart4_default>;
618 reg = <0xf9964000 0x1000>;
623 pinctrl-0 = <&blsp2_i2c2_default>;
626 #size-cells = <0>;
632 reg = <0xf9967000 0x1000>;
639 pinctrl-0 = <&blsp2_i2c5_default>;
642 #size-cells = <0>;
648 reg = <0xf9968000 0x1000>;
649 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
653 pinctrl-0 = <&blsp2_i2c6_default>;
656 #size-cells = <0>;
661 reg = <0xf9a55000 0x200>,
662 <0xf9a55200 0x200>;
673 ahb-burst-config = <0>;
679 usb_hs1_phy: phy-0 {
682 #phy-cells = <0>;
685 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
693 #phy-cells = <0>;
705 reg = <0xf9bff000 0x200>;
712 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
718 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
724 qcom,smem-states = <&wcnss_smp2p_out 0>;
770 reg = <0xfc190000 0x10000>;
775 reg = <0xfc307000 0x1000>;
799 reg = <0xfc318000 0x1000>;
815 reg = <0xfc31a000 0x1000>;
822 #size-cells = <0>;
826 * 0 - not-connected
853 reg = <0xfc31b000 0x1000>;
860 #size-cells = <0>;
864 * 0 - connected trought funnel to Audio, Modem and
887 reg = <0xfc31c000 0x1000>;
894 #size-cells = <0>;
896 port@0 {
897 reg = <0>;
921 reg = <0xfc322000 0x1000>;
937 reg = <0xfc33c000 0x1000>;
955 reg = <0xfc33d000 0x1000>;
973 reg = <0xfc33e000 0x1000>;
991 reg = <0xfc33f000 0x1000>;
1010 reg = <0xfc345000 0x1000>;
1017 #size-cells = <0>;
1019 port@0 {
1020 reg = <0>;
1059 reg = <0xfc400000 0x4000>;
1069 reg = <0xfc428000 0x4000>;
1073 reg = <0xfc380000 0x6a000>;
1082 reg = <0xfc460000 0x4000>;
1091 reg = <0xfc468000 0x4000>;
1100 reg = <0xfc470000 0x4000>;
1109 reg = <0xfc478000 0x4000>;
1118 reg = <0xfc480000 0x4000>;
1128 reg = <0xfc4a9000 0x1000>, /* TM */
1129 <0xfc4a8000 0x1000>; /* SROT */
1192 reg = <0xfc4ab000 0x4>;
1197 reg = <0xfc4bc000 0x2100>;
1202 reg = <0xd0 0x1>;
1203 bits = <0 8>;
1207 reg = <0xd1 0x1>;
1208 bits = <0 6>;
1212 reg = <0xd1 0x2>;
1217 reg = <0xd2 0x2>;
1222 reg = <0xd3 0x1>;
1227 reg = <0xd4 0x1>;
1228 bits = <0 6>;
1232 reg = <0xd4 0x2>;
1237 reg = <0xd5 0x2>;
1242 reg = <0xd6 0x1>;
1247 reg = <0xd7 0x1>;
1248 bits = <0 6>;
1252 reg = <0xd7 0x1>;
1257 reg = <0xd8 0x1>;
1258 bits = <0 6>;
1262 reg = <0xd8 0x2>;
1267 reg = <0xd9 0x2>;
1272 reg = <0xda 0x2>;
1277 reg = <0xdb 0x1>;
1282 reg = <0xdc 0x1>;
1283 bits = <0 6>;
1287 reg = <0xdc 0x2>;
1292 reg = <0xdd 0x2>;
1297 reg = <0xde 0x2>;
1302 reg = <0xdf 0x1>;
1303 bits = <0 6>;
1307 reg = <0xe0 0x1>;
1308 bits = <0 6>;
1312 reg = <0xe0 0x2>;
1317 reg = <0xe1 0x2>;
1322 reg = <0xe2 0x2>;
1327 reg = <0xe3 0x2>;
1328 bits = <0 6>;
1332 reg = <0xe3 0x1>;
1337 reg = <0xe4 0x1>;
1338 bits = <0 6>;
1342 reg = <0xe4 0x2>;
1347 reg = <0xe5 0x2>;
1352 reg = <0xe6 0x2>;
1357 reg = <0xe7 0x1>;
1358 bits = <0 6>;
1362 reg = <0x440 0x1>;
1363 bits = <0 8>;
1367 reg = <0x441 0x1>;
1368 bits = <0 6>;
1372 reg = <0x441 0x2>;
1377 reg = <0x442 0x2>;
1382 reg = <0x443 0x1>;
1387 reg = <0x444 0x1>;
1388 bits = <0 6>;
1392 reg = <0x444 0x2>;
1397 reg = <0x445 0x2>;
1402 reg = <0x446 0x1>;
1407 reg = <0x447 0x1>;
1412 reg = <0x448 0x1>;
1413 bits = <0 6>;
1417 reg = <0x448 0x2>;
1422 reg = <0x449 0x2>;
1427 reg = <0x44a 0x2>;
1432 reg = <0x44b 0x3>;
1437 reg = <0x44c 0x1>;
1438 bits = <0 6>;
1442 reg = <0x44c 0x2>;
1447 reg = <0x44d 0x2>;
1452 reg = <0x44e 0x1>;
1460 reg = <0xfc4cf000 0x1000>,
1461 <0xfc4cb000 0x1000>,
1462 <0xfc4ca000 0x1000>;
1465 qcom,ee = <0>;
1466 qcom,channel = <0>;
1468 #size-cells = <0>;
1475 reg = <0xfc834000 0x7000>;
1478 qcom,ee = <0>;
1487 reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
1491 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1506 qcom,halt-regs = <&tcsr_mutex 0x1180 0x1200 0x1280>;
1508 qcom,smem-states = <&modem_smp2p_out 0>;
1539 qcom,smd-edge = <0>;
1547 reg = <0xfd484000 0x2000>;
1553 reg = <0xfd4a0000 0x10000>;
1558 reg = <0xfd510000 0x4000>;
1560 gpio-ranges = <&tlmm 0 0 146>;
1834 reg = <0xfd8c0000 0x6000>;
1841 <&mdss_dsi0_phy 0>,
1843 <&mdss_dsi1_phy 0>,
1844 <0>,
1845 <0>,
1846 <0>;
1863 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
1886 reg = <0xfd900100 0x22000>;
1890 interrupts = <0>;
1903 #size-cells = <0>;
1905 port@0 {
1906 reg = <0>;
1924 reg = <0xfd922800 0x1f8>;
1931 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1953 #size-cells = <0>;
1957 #size-cells = <0>;
1959 port@0 {
1960 reg = <0>;
1976 reg = <0xfd922a00 0xd4>,
1977 <0xfd922b00 0x280>,
1978 <0xfd922d80 0x30>;
1984 #phy-cells = <0>;
1995 reg = <0xfd922e00 0x1f8>;
2002 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
2024 #size-cells = <0>;
2028 #size-cells = <0>;
2030 port@0 {
2031 reg = <0>;
2047 reg = <0xfd923000 0xd4>,
2048 <0xfd923100 0x280>,
2049 <0xfd923380 0x30>;
2055 #phy-cells = <0>;
2067 #size-cells = <0>;
2068 reg = <0xfda0c000 0x1000>;
2078 pinctrl-0 = <&cci_default>;
2083 cci_i2c0: i2c-bus@0 {
2084 reg = <0>;
2087 #size-cells = <0>;
2094 #size-cells = <0>;
2100 reg = <0xfdb00000 0x10000>;
2119 // iommus = <&gpu_iommu 0>;
2142 reg = <0xfdd00000 0x2000>,
2143 <0xfec00000 0x180000>;
2145 ranges = <0 0xfec00000 0x180000>;
2153 gmu_sram: gmu-sram@0 {
2154 reg = <0x0 0x100000>;
2160 reg = <0xfe200000 0x100>;
2163 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2174 qcom,smem-states = <&adsp_smp2p_out 0>;
2190 reg = <0xfe805000 0x1000>;
2194 offset = <0x65c>;
2373 interrupts = <GIC_PPI 2 0xf08>,
2374 <GIC_PPI 3 0xf08>,
2375 <GIC_PPI 4 0xf08>,
2376 <GIC_PPI 1 0xf08>;
2394 pinctrl-0 = <&boost_bypass_n_pin>;