Lines Matching +full:dsi +full:- +full:phy +full:- +full:10 +full:nm
1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
10 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
19 interrupt-parent = <&intc>;
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <19200000>;
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32768>;
44 compatible = "qcom,scm-msm8226", "qcom,scm";
46 clock-names = "core", "bus", "iface";
51 compatible = "arm,cortex-a7-pmu";
57 compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc";
59 smd-edge {
62 qcom,smd-edge = <15>;
64 rpm_requests: rpm-requests {
65 compatible = "qcom,rpm-msm8226";
66 qcom,smd-channels = "rpm_requests";
68 rpmcc: clock-controller {
69 compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc";
70 #clock-cells = <1>;
72 clock-names = "xo";
75 rpmpd: power-controller {
76 compatible = "qcom,msm8226-rpmpd";
77 #power-domain-cells = <1>;
78 operating-points-v2 = <&rpmpd_opp_table>;
80 rpmpd_opp_table: opp-table {
81 compatible = "operating-points-v2";
84 opp-level = <1>;
87 opp-level = <2>;
90 opp-level = <3>;
93 opp-level = <4>;
96 opp-level = <5>;
99 opp-level = <6>;
107 reserved-memory {
108 #address-cells = <1>;
109 #size-cells = <1>;
114 no-map;
119 no-map;
126 memory-region = <&smem_region>;
127 qcom,rpm-msg-ram = <&rpm_msg_ram>;
132 smp2p-adsp {
136 interrupt-parent = <&intc>;
139 qcom,ipc = <&apcs 8 10>;
141 qcom,local-pid = <0>;
142 qcom,remote-pid = <2>;
144 adsp_smp2p_out: master-kernel {
145 qcom,entry-name = "master-kernel";
146 #qcom,smem-state-cells = <1>;
149 adsp_smp2p_in: slave-kernel {
150 qcom,entry-name = "slave-kernel";
152 interrupt-controller;
153 #interrupt-cells = <2>;
158 compatible = "simple-bus";
159 #address-cells = <1>;
160 #size-cells = <1>;
163 intc: interrupt-controller@f9000000 {
164 compatible = "qcom,msm-qgic2";
167 interrupt-controller;
168 #interrupt-cells = <3>;
177 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
179 reg-names = "hc", "core";
182 interrupt-names = "hc_irq", "pwr_irq";
186 clock-names = "iface", "core", "xo";
187 pinctrl-names = "default";
188 pinctrl-0 = <&sdhc1_default_state>;
193 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
195 reg-names = "hc", "core";
198 interrupt-names = "hc_irq", "pwr_irq";
202 clock-names = "iface", "core", "xo";
203 pinctrl-names = "default";
204 pinctrl-0 = <&sdhc2_default_state>;
209 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
211 reg-names = "hc", "core";
214 interrupt-names = "hc_irq", "pwr_irq";
218 clock-names = "iface", "core", "xo";
219 pinctrl-names = "default";
220 pinctrl-0 = <&sdhc3_default_state>;
225 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
229 clock-names = "core", "iface";
234 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
238 clock-names = "core", "iface";
243 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
247 clock-names = "core", "iface";
253 compatible = "qcom,i2c-qup-v2.1.1";
257 clock-names = "core", "iface";
258 pinctrl-names = "default";
259 pinctrl-0 = <&blsp1_i2c1_pins>;
260 #address-cells = <1>;
261 #size-cells = <0>;
266 compatible = "qcom,i2c-qup-v2.1.1";
270 clock-names = "core", "iface";
271 pinctrl-names = "default";
272 pinctrl-0 = <&blsp1_i2c2_pins>;
273 #address-cells = <1>;
274 #size-cells = <0>;
279 compatible = "qcom,i2c-qup-v2.1.1";
283 clock-names = "core", "iface";
284 pinctrl-names = "default";
285 pinctrl-0 = <&blsp1_i2c3_pins>;
286 #address-cells = <1>;
287 #size-cells = <0>;
292 compatible = "qcom,i2c-qup-v2.1.1";
296 clock-names = "core", "iface";
297 pinctrl-names = "default";
298 pinctrl-0 = <&blsp1_i2c4_pins>;
299 #address-cells = <1>;
300 #size-cells = <0>;
305 compatible = "qcom,i2c-qup-v2.1.1";
309 clock-names = "core", "iface";
310 pinctrl-names = "default";
311 pinctrl-0 = <&blsp1_i2c5_pins>;
312 #address-cells = <1>;
313 #size-cells = <0>;
317 compatible = "qcom,msm8226-cci";
318 #address-cells = <1>;
319 #size-cells = <0>;
325 clock-names = "camss_top_ahb",
329 pinctrl-names = "default", "sleep";
330 pinctrl-0 = <&cci_default>;
331 pinctrl-1 = <&cci_sleep>;
335 cci_i2c0: i2c-bus@0 {
337 clock-frequency = <400000>;
338 #address-cells = <1>;
339 #size-cells = <0>;
344 compatible = "qcom,ci-hdrc";
350 clock-names = "iface", "core";
351 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
352 assigned-clock-rates = <75000000>;
354 reset-names = "core";
357 hnp-disable;
358 srp-disable;
359 adp-disable;
360 ahb-burst-config = <0>;
361 phy-names = "usb-phy";
364 #reset-cells = <1>;
367 usb_hs_phy: phy {
368 compatible = "qcom,usb-hs-phy-msm8226",
369 "qcom,usb-hs-phy";
370 #phy-cells = <0>;
373 clock-names = "ref", "sleep";
375 reset-names = "phy", "por";
376 qcom,init-seq = /bits/ 8 <0x0 0x44
382 gcc: clock-controller@fc400000 {
383 compatible = "qcom,gcc-msm8226";
385 #clock-cells = <1>;
386 #reset-cells = <1>;
387 #power-domain-cells = <1>;
391 clock-names = "xo",
395 mmcc: clock-controller@fd8c0000 {
396 compatible = "qcom,mmcc-msm8226";
398 #clock-cells = <1>;
399 #reset-cells = <1>;
400 #power-domain-cells = <1>;
409 clock-names = "xo",
419 compatible = "qcom,msm8226-pinctrl";
421 gpio-controller;
422 #gpio-cells = <2>;
423 gpio-ranges = <&tlmm 0 0 117>;
424 interrupt-controller;
425 #interrupt-cells = <2>;
428 blsp1_i2c1_pins: blsp1-i2c1-state {
431 drive-strength = <2>;
432 bias-disable;
435 blsp1_i2c2_pins: blsp1-i2c2-state {
438 drive-strength = <2>;
439 bias-disable;
442 blsp1_i2c3_pins: blsp1-i2c3-state {
445 drive-strength = <2>;
446 bias-disable;
449 blsp1_i2c4_pins: blsp1-i2c4-state {
452 drive-strength = <2>;
453 bias-disable;
456 blsp1_i2c5_pins: blsp1-i2c5-state {
459 drive-strength = <2>;
460 bias-disable;
463 cci_default: cci-default-state {
467 drive-strength = <2>;
468 bias-disable;
471 cci_sleep: cci-sleep-state {
475 drive-strength = <2>;
476 bias-disable;
479 sdhc1_default_state: sdhc1-default-state {
480 clk-pins {
482 drive-strength = <10>;
483 bias-disable;
486 cmd-data-pins {
488 drive-strength = <10>;
489 bias-pull-up;
493 sdhc2_default_state: sdhc2-default-state {
494 clk-pins {
496 drive-strength = <10>;
497 bias-disable;
500 cmd-data-pins {
502 drive-strength = <10>;
503 bias-pull-up;
507 sdhc3_default_state: sdhc3-default-state {
508 clk-pins {
511 drive-strength = <8>;
512 bias-disable;
515 cmd-pins {
518 drive-strength = <8>;
519 bias-pull-up;
522 data-pins {
525 drive-strength = <8>;
526 bias-pull-up;
531 tsens: thermal-sensor@fc4a9000 {
532 compatible = "qcom,msm8226-tsens", "qcom,tsens-v0_1";
535 nvmem-cells = <&tsens_mode>,
544 nvmem-cell-names = "mode",
555 interrupt-names = "uplow";
556 #thermal-sensor-cells = <1>;
565 compatible = "qcom,msm8226-qfprom", "qcom,qfprom";
567 #address-cells = <1>;
568 #size-cells = <1>;
575 tsens_s0_p1: s0-p1@1c2 {
580 tsens_s1_p1: s1-p1@1c4 {
585 tsens_s2_p1: s2-p1@1c4 {
590 tsens_s3_p1: s3-p1@1c5 {
595 tsens_s4_p1: s4-p1@1c6 {
600 tsens_s5_p1: s5-p1@1c7 {
605 tsens_s6_p1: s6-p1@1ca {
615 tsens_s0_p2: s0-p2@1cd {
620 tsens_s1_p2: s1-p2@1cd {
625 tsens_s2_p2: s2-p2@1ce {
630 tsens_s3_p2: s3-p2@1cf {
635 tsens_s4_p2: s4-p2@446 {
640 tsens_s5_p2: s5-p2@447 {
645 tsens_s6_p2: s6-p2@44e {
657 compatible = "qcom,spmi-pmic-arb";
658 reg-names = "core", "intr", "cnfg";
662 interrupt-names = "periph_irq";
666 #address-cells = <2>;
667 #size-cells = <0>;
668 interrupt-controller;
669 #interrupt-cells = <4>;
676 clock-names = "core";
680 compatible = "arm,armv7-timer-mem";
682 #address-cells = <1>;
683 #size-cells = <1>;
687 frame-number = <0>;
695 frame-number = <1>;
702 frame-number = <2>;
703 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
709 frame-number = <3>;
716 frame-number = <4>;
723 frame-number = <5>;
730 frame-number = <6>;
738 compatible = "qcom,msm8226-rpm-stats";
743 compatible = "qcom,rpm-msg-ram";
748 compatible = "qcom,msm8226-tcsr-mutex", "qcom,tcsr-mutex";
750 #hwlock-cells = <1>;
754 compatible = "qcom,msm8226-adsp-pil";
757 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
762 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
764 power-domains = <&rpmpd MSM8226_VDDCX>;
765 power-domain-names = "cx";
768 clock-names = "xo";
770 memory-region = <&adsp_region>;
772 qcom,smem-states = <&adsp_smp2p_out 0>;
773 qcom,smem-state-names = "stop";
777 smd-edge {
781 qcom,smd-edge = <1>;
788 compatible = "qcom,msm8226-ocmem";
791 reg-names = "ctrl", "mem";
794 clock-names = "core";
796 #address-cells = <1>;
797 #size-cells = <1>;
799 gmu_sram: gmu-sram@0 {
805 compatible = "qcom,msm8226-imem", "syscon", "simple-mfd";
808 reboot-mode {
809 compatible = "syscon-reboot-mode";
812 mode-bootloader = <0x77665500>;
813 mode-normal = <0x77665501>;
814 mode-recovery = <0x77665502>;
818 mdss: display-subsystem@fd900000 {
821 reg-names = "mdss_phys", "vbif_phys";
823 power-domains = <&mmcc MDSS_GDSC>;
828 clock-names = "iface",
834 interrupt-controller;
835 #interrupt-cells = <1>;
837 #address-cells = <1>;
838 #size-cells = <1>;
843 mdss_mdp: display-controller@fd900000 {
844 compatible = "qcom,msm8226-mdp5", "qcom,mdp5";
846 reg-names = "mdp_phys";
848 interrupt-parent = <&mdss>;
855 clock-names = "iface",
861 #address-cells = <1>;
862 #size-cells = <0>;
867 remote-endpoint = <&mdss_dsi0_in>;
873 mdss_dsi0: dsi@fd922800 {
874 compatible = "qcom,msm8226-dsi-ctrl",
875 "qcom,mdss-dsi-ctrl";
877 reg-names = "dsi_ctrl";
879 interrupt-parent = <&mdss>;
882 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
884 assigned-clock-parents = <&mdss_dsi0_phy 0>,
894 clock-names = "mdp_core",
904 #address-cells = <1>;
905 #size-cells = <0>;
908 #address-cells = <1>;
909 #size-cells = <0>;
914 remote-endpoint = <&mdss_mdp_intf1_out>;
926 mdss_dsi0_phy: phy@fd922a00 {
927 compatible = "qcom,dsi-phy-28nm-8226";
931 reg-names = "dsi_pll",
935 #clock-cells = <1>;
936 #phy-cells = <0>;
940 clock-names = "iface",
946 thermal-zones {
947 cpu0-thermal {
948 polling-delay-passive = <250>;
949 polling-delay = <1000>;
951 thermal-sensors = <&tsens 5>;
968 cpu1-thermal {
969 polling-delay-passive = <250>;
970 polling-delay = <1000>;
972 thermal-sensors = <&tsens 2>;
991 compatible = "arm,armv7-timer";