Lines Matching +full:0 +full:xfc400000
23 memory@0 {
25 reg = <0x0 0x0>;
31 #clock-cells = <0>;
37 #clock-cells = <0>;
61 qcom,ipc = <&apcs 8 0>;
113 reg = <0x3000000 0x100000>;
118 reg = <0x0dc00000 0x1900000>;
141 qcom,local-pid = <0>;
165 reg = <0xf9000000 0x1000>,
166 <0xf9002000 0x1000>;
173 reg = <0xf9011000 0x1000>;
178 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
188 pinctrl-0 = <&sdhc1_default_state>;
194 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
204 pinctrl-0 = <&sdhc2_default_state>;
210 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
220 pinctrl-0 = <&sdhc3_default_state>;
226 reg = <0xf991d000 0x1000>;
235 reg = <0xf991f000 0x1000>;
244 reg = <0xf9920000 0x1000>;
254 reg = <0xf9923000 0x1000>;
259 pinctrl-0 = <&blsp1_i2c1_pins>;
261 #size-cells = <0>;
267 reg = <0xf9924000 0x1000>;
272 pinctrl-0 = <&blsp1_i2c2_pins>;
274 #size-cells = <0>;
280 reg = <0xf9925000 0x1000>;
285 pinctrl-0 = <&blsp1_i2c3_pins>;
287 #size-cells = <0>;
293 reg = <0xf9926000 0x1000>;
298 pinctrl-0 = <&blsp1_i2c4_pins>;
300 #size-cells = <0>;
306 reg = <0xf9927000 0x1000>;
311 pinctrl-0 = <&blsp1_i2c5_pins>;
313 #size-cells = <0>;
319 #size-cells = <0>;
320 reg = <0xfda0c000 0x1000>;
330 pinctrl-0 = <&cci_default>;
335 cci_i2c0: i2c-bus@0 {
336 reg = <0>;
339 #size-cells = <0>;
345 reg = <0xf9a55000 0x200>,
346 <0xf9a55200 0x200>;
360 ahb-burst-config = <0>;
370 #phy-cells = <0>;
374 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
376 qcom,init-seq = /bits/ 8 <0x0 0x44
377 0x1 0x68 0x2 0x24 0x3 0x13>;
384 reg = <0xfc400000 0x4000>;
397 reg = <0xfd8c0000 0x6000>;
408 <&mdss_dsi0_phy 0>;
420 reg = <0xfd510000 0x4000>;
423 gpio-ranges = <&tlmm 0 0 117>;
533 reg = <0xfc4a9000 0x1000>, /* TM */
534 <0xfc4a8000 0x1000>; /* SROT */
561 reg = <0xfc4ab000 0x4>;
566 reg = <0xfc4bc000 0x1000>;
571 reg = <0x1c1 0x2>;
576 reg = <0x1c2 0x2>;
581 reg = <0x1c4 0x1>;
582 bits = <0 6>;
586 reg = <0x1c4 0x2>;
591 reg = <0x1c5 0x2>;
596 reg = <0x1c6 0x1>;
601 reg = <0x1c7 0x1>;
602 bits = <0 6>;
606 reg = <0x1ca 0x2>;
611 reg = <0x1cc 0x1>;
612 bits = <0 8>;
616 reg = <0x1cd 0x1>;
617 bits = <0 6>;
621 reg = <0x1cd 0x2>;
626 reg = <0x1ce 0x2>;
631 reg = <0x1cf 0x1>;
636 reg = <0x446 0x2>;
641 reg = <0x447 0x1>;
646 reg = <0x44e 0x1>;
651 reg = <0x44f 0x1>;
659 reg = <0xfc4cf000 0x1000>,
660 <0xfc4cb000 0x1000>,
661 <0xfc4ca000 0x1000>;
664 qcom,ee = <0>;
665 qcom,channel = <0>;
667 #size-cells = <0>;
674 reg = <0xf9bff000 0x200>;
681 reg = <0xf9020000 0x1000>;
687 frame-number = <0>;
690 reg = <0xf9021000 0x1000>,
691 <0xf9022000 0x1000>;
697 reg = <0xf9023000 0x1000>;
704 reg = <0xf9024000 0x1000>;
711 reg = <0xf9025000 0x1000>;
718 reg = <0xf9026000 0x1000>;
725 reg = <0xf9027000 0x1000>;
732 reg = <0xf9028000 0x1000>;
739 reg = <0xfc190000 0x10000>;
744 reg = <0xfc428000 0x4000>;
749 reg = <0xfd484000 0x1000>;
755 reg = <0xfe200000 0x100>;
758 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
772 qcom,smem-states = <&adsp_smp2p_out 0>;
789 reg = <0xfdd00000 0x2000>,
790 <0xfec00000 0x20000>;
792 ranges = <0 0xfec00000 0x20000>;
799 gmu_sram: gmu-sram@0 {
800 reg = <0x0 0x20000>;
806 reg = <0xfe805000 0x1000>;
810 offset = <0x65c>;
812 mode-bootloader = <0x77665500>;
813 mode-normal = <0x77665501>;
814 mode-recovery = <0x77665502>;
820 reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;
845 reg = <0xfd900100 0x22000>;
849 interrupts = <0>;
862 #size-cells = <0>;
864 port@0 {
865 reg = <0>;
876 reg = <0xfd922800 0x1f8>;
884 assigned-clock-parents = <&mdss_dsi0_phy 0>,
905 #size-cells = <0>;
909 #size-cells = <0>;
911 port@0 {
912 reg = <0>;
928 reg = <0xfd922a00 0xd4>,
929 <0xfd922b00 0x280>,
930 <0xfd922d80 0x30>;
936 #phy-cells = <0>;