Lines Matching +full:gcc +full:- +full:ipq4019
1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 model = "Qualcomm Technologies, Inc. IPQ4019";
17 compatible = "qcom,ipq4019";
18 interrupt-parent = <&intc>;
20 reserved-memory {
21 #address-cells = <0x1>;
22 #size-cells = <0x1>;
27 no-map;
32 no-map;
44 #address-cells = <1>;
45 #size-cells = <0>;
48 compatible = "arm,cortex-a7";
49 enable-method = "qcom,kpss-acc-v2";
50 next-level-cache = <&L2>;
54 clocks = <&gcc GCC_APPS_CLK_SRC>;
55 clock-frequency = <0>;
56 clock-latency = <256000>;
57 operating-points-v2 = <&cpu0_opp_table>;
62 compatible = "arm,cortex-a7";
63 enable-method = "qcom,kpss-acc-v2";
64 next-level-cache = <&L2>;
68 clocks = <&gcc GCC_APPS_CLK_SRC>;
69 clock-frequency = <0>;
70 clock-latency = <256000>;
71 operating-points-v2 = <&cpu0_opp_table>;
76 compatible = "arm,cortex-a7";
77 enable-method = "qcom,kpss-acc-v2";
78 next-level-cache = <&L2>;
82 clocks = <&gcc GCC_APPS_CLK_SRC>;
83 clock-frequency = <0>;
84 clock-latency = <256000>;
85 operating-points-v2 = <&cpu0_opp_table>;
90 compatible = "arm,cortex-a7";
91 enable-method = "qcom,kpss-acc-v2";
92 next-level-cache = <&L2>;
96 clocks = <&gcc GCC_APPS_CLK_SRC>;
97 clock-frequency = <0>;
98 clock-latency = <256000>;
99 operating-points-v2 = <&cpu0_opp_table>;
102 L2: l2-cache {
104 cache-level = <2>;
105 cache-unified;
110 cpu0_opp_table: opp-table {
111 compatible = "operating-points-v2";
112 opp-shared;
114 opp-48000000 {
115 opp-hz = /bits/ 64 <48000000>;
116 clock-latency-ns = <256000>;
118 opp-200000000 {
119 opp-hz = /bits/ 64 <200000000>;
120 clock-latency-ns = <256000>;
122 opp-500000000 {
123 opp-hz = /bits/ 64 <500000000>;
124 clock-latency-ns = <256000>;
126 opp-716000000 {
127 opp-hz = /bits/ 64 <716000000>;
128 clock-latency-ns = <256000>;
138 compatible = "arm,cortex-a7-pmu";
145 compatible = "fixed-clock";
146 clock-frequency = <32000>;
147 #clock-cells = <0>;
151 compatible = "fixed-clock";
152 clock-frequency = <48000000>;
153 #clock-cells = <0>;
159 compatible = "qcom,scm-ipq4019", "qcom,scm";
164 compatible = "arm,armv7-timer";
169 clock-frequency = <48000000>;
170 always-on;
174 #address-cells = <1>;
175 #size-cells = <1>;
177 compatible = "simple-bus";
179 intc: interrupt-controller@b000000 {
180 compatible = "qcom,msm-qgic2";
181 interrupt-controller;
182 #interrupt-cells = <3>;
187 gcc: clock-controller@1800000 { label
188 compatible = "qcom,gcc-ipq4019";
189 #clock-cells = <1>;
190 #power-domain-cells = <1>;
191 #reset-cells = <1>;
194 clock-names = "xo", "sleep_clk";
200 clocks = <&gcc GCC_PRNG_AHB_CLK>;
201 clock-names = "core";
206 compatible = "qcom,ipq4019-pinctrl";
208 gpio-controller;
209 gpio-ranges = <&tlmm 0 0 100>;
210 #gpio-cells = <2>;
211 interrupt-controller;
212 #interrupt-cells = <2>;
217 compatible = "qcom,vqmmc-ipq4019-regulator";
219 regulator-name = "vqmmc";
220 regulator-min-microvolt = <1500000>;
221 regulator-max-microvolt = <3000000>;
222 regulator-always-on;
227 compatible = "qcom,sdhci-msm-v4";
229 reg-names = "hc", "core";
231 interrupt-names = "hc_irq", "pwr_irq";
232 bus-width = <8>;
233 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
234 <&gcc GCC_SDCC1_APPS_CLK>,
236 clock-names = "iface",
242 blsp_dma: dma-controller@7884000 {
243 compatible = "qcom,bam-v1.7.0";
246 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
247 clock-names = "bam_clk";
248 #dma-cells = <1>;
254 compatible = "qcom,spi-qup-v2.2.1";
257 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
258 <&gcc GCC_BLSP1_AHB_CLK>;
259 clock-names = "core", "iface";
260 #address-cells = <1>;
261 #size-cells = <0>;
263 dma-names = "tx", "rx";
268 compatible = "qcom,spi-qup-v2.2.1";
271 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
272 <&gcc GCC_BLSP1_AHB_CLK>;
273 clock-names = "core", "iface";
274 #address-cells = <1>;
275 #size-cells = <0>;
277 dma-names = "tx", "rx";
282 compatible = "qcom,i2c-qup-v2.2.1";
285 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
286 <&gcc GCC_BLSP1_AHB_CLK>;
287 clock-names = "core", "iface";
288 #address-cells = <1>;
289 #size-cells = <0>;
291 dma-names = "tx", "rx";
296 compatible = "qcom,i2c-qup-v2.2.1";
299 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
300 <&gcc GCC_BLSP1_AHB_CLK>;
301 clock-names = "core", "iface";
302 #address-cells = <1>;
303 #size-cells = <0>;
305 dma-names = "tx", "rx";
309 cryptobam: dma-controller@8e04000 {
310 compatible = "qcom,bam-v1.7.0";
313 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
314 clock-names = "bam_clk";
315 #dma-cells = <1>;
317 qcom,controlled-remotely;
322 compatible = "qcom,crypto-v5.1";
324 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
325 <&gcc GCC_CRYPTO_AXI_CLK>,
326 <&gcc GCC_CRYPTO_CLK>;
327 clock-names = "iface", "bus", "core";
329 dma-names = "rx", "tx";
333 acc0: power-manager@b088000 {
334 compatible = "qcom,kpss-acc-v2";
338 acc1: power-manager@b098000 {
339 compatible = "qcom,kpss-acc-v2";
343 acc2: power-manager@b0a8000 {
344 compatible = "qcom,kpss-acc-v2";
348 acc3: power-manager@b0b8000 {
349 compatible = "qcom,kpss-acc-v2";
384 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
388 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
389 <&gcc GCC_BLSP1_AHB_CLK>;
390 clock-names = "core", "iface";
392 dma-names = "tx", "rx";
396 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
400 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
401 <&gcc GCC_BLSP1_AHB_CLK>;
402 clock-names = "core", "iface";
404 dma-names = "tx", "rx";
408 compatible = "qcom,kpss-wdt-ipq4019", "qcom,kpss-wdt";
411 timeout-sec = <10>;
421 compatible = "qcom,pcie-ipq4019";
426 reg-names = "dbi", "elbi", "parf", "config";
428 linux,pci-domain = <0>;
429 bus-range = <0x00 0xff>;
430 num-lanes = <1>;
431 #address-cells = <3>;
432 #size-cells = <2>;
438 interrupt-names = "msi";
439 #interrupt-cells = <1>;
440 interrupt-map-mask = <0 0 0 0x7>;
441 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
445 clocks = <&gcc GCC_PCIE_AHB_CLK>,
446 <&gcc GCC_PCIE_AXI_M_CLK>,
447 <&gcc GCC_PCIE_AXI_S_CLK>;
448 clock-names = "aux",
452 resets = <&gcc PCIE_AXI_M_ARES>,
453 <&gcc PCIE_AXI_S_ARES>,
454 <&gcc PCIE_PIPE_ARES>,
455 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
456 <&gcc PCIE_AXI_S_XPU_ARES>,
457 <&gcc PCIE_PARF_XPU_ARES>,
458 <&gcc PCIE_PHY_ARES>,
459 <&gcc PCIE_AXI_M_STICKY_ARES>,
460 <&gcc PCIE_PIPE_STICKY_ARES>,
461 <&gcc PCIE_PWR_ARES>,
462 <&gcc PCIE_AHB_ARES>,
463 <&gcc PCIE_PHY_AHB_ARES>;
464 reset-names = "axi_m",
480 qpic_bam: dma-controller@7984000 {
481 compatible = "qcom,bam-v1.7.0";
484 clocks = <&gcc GCC_QPIC_CLK>;
485 clock-names = "bam_clk";
486 #dma-cells = <1>;
491 nand: nand-controller@79b0000 {
492 compatible = "qcom,ipq4019-nand";
494 #address-cells = <1>;
495 #size-cells = <0>;
496 clocks = <&gcc GCC_QPIC_CLK>,
497 <&gcc GCC_QPIC_AHB_CLK>;
498 clock-names = "core", "aon";
503 dma-names = "tx", "rx", "cmd";
509 nand-ecc-strength = <4>;
510 nand-ecc-step-size = <512>;
511 nand-bus-width = <8>;
516 compatible = "qcom,ipq4019-wifi";
518 resets = <&gcc WIFI0_CPU_INIT_RESET>,
519 <&gcc WIFI0_RADIO_SRIF_RESET>,
520 <&gcc WIFI0_RADIO_WARM_RESET>,
521 <&gcc WIFI0_RADIO_COLD_RESET>,
522 <&gcc WIFI0_CORE_WARM_RESET>,
523 <&gcc WIFI0_CORE_COLD_RESET>;
524 reset-names = "wifi_cpu_init", "wifi_radio_srif",
527 clocks = <&gcc GCC_WCSS2G_CLK>,
528 <&gcc GCC_WCSS2G_REF_CLK>,
529 <&gcc GCC_WCSS2G_RTC_CLK>;
530 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
549 interrupt-names = "msi0", "msi1", "msi2", "msi3",
558 compatible = "qcom,ipq4019-wifi";
560 resets = <&gcc WIFI1_CPU_INIT_RESET>,
561 <&gcc WIFI1_RADIO_SRIF_RESET>,
562 <&gcc WIFI1_RADIO_WARM_RESET>,
563 <&gcc WIFI1_RADIO_COLD_RESET>,
564 <&gcc WIFI1_CORE_WARM_RESET>,
565 <&gcc WIFI1_CORE_COLD_RESET>;
566 reset-names = "wifi_cpu_init", "wifi_radio_srif",
569 clocks = <&gcc GCC_WCSS5G_CLK>,
570 <&gcc GCC_WCSS5G_REF_CLK>,
571 <&gcc GCC_WCSS5G_RTC_CLK>;
572 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
591 interrupt-names = "msi0", "msi1", "msi2", "msi3",
600 #address-cells = <1>;
601 #size-cells = <0>;
602 compatible = "qcom,ipq4019-mdio";
606 ethphy0: ethernet-phy@0 {
610 ethphy1: ethernet-phy@1 {
614 ethphy2: ethernet-phy@2 {
618 ethphy3: ethernet-phy@3 {
622 ethphy4: ethernet-phy@4 {
627 usb3_ss_phy: usb-phy@9a000 {
628 compatible = "qcom,usb-ss-ipq4019-phy";
629 #phy-cells = <0>;
631 reg-names = "phy_base";
632 resets = <&gcc USB3_UNIPHY_PHY_ARES>;
633 reset-names = "por_rst";
637 usb3_hs_phy: usb-phy@a6000 {
638 compatible = "qcom,usb-hs-ipq4019-phy";
639 #phy-cells = <0>;
641 reg-names = "phy_base";
642 resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
643 reset-names = "por_rst", "srif_rst";
648 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
650 #address-cells = <1>;
651 #size-cells = <1>;
652 clocks = <&gcc GCC_USB3_MASTER_CLK>,
653 <&gcc GCC_USB3_SLEEP_CLK>,
654 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
655 clock-names = "core", "sleep", "mock_utmi";
664 phy-names = "usb2-phy", "usb3-phy";
669 usb2_hs_phy: usb-phy@a8000 {
670 compatible = "qcom,usb-hs-ipq4019-phy";
671 #phy-cells = <0>;
673 reg-names = "phy_base";
674 resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
675 reset-names = "por_rst", "srif_rst";
680 compatible = "qcom,ipq4019-dwc3", "qcom,dwc3";
682 #address-cells = <1>;
683 #size-cells = <1>;
684 clocks = <&gcc GCC_USB2_MASTER_CLK>,
685 <&gcc GCC_USB2_SLEEP_CLK>,
686 <&gcc GCC_USB2_MOCK_UTMI_CLK>;
687 clock-names = "master", "sleep", "mock_utmi";
696 phy-names = "usb2-phy";