Lines Matching +full:bam +full:- +full:v1
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
17 interrupt-parent = <&intc>;
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
26 no-map;
31 no-map;
36 #address-cells = <1>;
37 #size-cells = <0>;
41 enable-method = "qcom,kpss-acc-v1";
44 next-level-cache = <&L2>;
47 cpu-idle-states = <&CPU_SPC>;
52 enable-method = "qcom,kpss-acc-v1";
55 next-level-cache = <&L2>;
58 cpu-idle-states = <&CPU_SPC>;
63 enable-method = "qcom,kpss-acc-v1";
66 next-level-cache = <&L2>;
69 cpu-idle-states = <&CPU_SPC>;
74 enable-method = "qcom,kpss-acc-v1";
77 next-level-cache = <&L2>;
80 cpu-idle-states = <&CPU_SPC>;
83 L2: l2-cache {
85 cache-level = <2>;
86 cache-unified;
89 idle-states {
91 compatible = "qcom,idle-state-spc",
92 "arm,idle-state";
93 entry-latency-us = <400>;
94 exit-latency-us = <900>;
95 min-residency-us = <3000>;
105 thermal-zones {
106 cpu0-thermal {
107 polling-delay-passive = <250>;
108 polling-delay = <1000>;
110 thermal-sensors = <&tsens 7>;
127 cpu1-thermal {
128 polling-delay-passive = <250>;
129 polling-delay = <1000>;
131 thermal-sensors = <&tsens 8>;
148 cpu2-thermal {
149 polling-delay-passive = <250>;
150 polling-delay = <1000>;
152 thermal-sensors = <&tsens 9>;
169 cpu3-thermal {
170 polling-delay-passive = <250>;
171 polling-delay = <1000>;
173 thermal-sensors = <&tsens 10>;
191 cpu-pmu {
192 compatible = "qcom,krait-pmu";
198 compatible = "fixed-clock";
199 #clock-cells = <0>;
200 clock-frequency = <19200000>;
204 compatible = "fixed-clock";
205 #clock-cells = <0>;
206 clock-frequency = <27000000>;
210 compatible = "fixed-clock";
211 #clock-cells = <0>;
212 clock-frequency = <32768>;
217 compatible = "qcom,sfpb-mutex";
219 #hwlock-cells = <1>;
224 memory-region = <&smem_region>;
232 #address-cells = <1>;
233 #size-cells = <0>;
235 qcom,ipc-1 = <&l2cc 8 4>;
236 qcom,ipc-2 = <&l2cc 8 14>;
237 qcom,ipc-3 = <&l2cc 8 23>;
238 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
242 #qcom,smem-state-cells = <1>;
249 interrupt-controller;
250 #interrupt-cells = <2>;
257 interrupt-controller;
258 #interrupt-cells = <2>;
265 interrupt-controller;
266 #interrupt-cells = <2>;
273 interrupt-controller;
274 #interrupt-cells = <2>;
280 compatible = "qcom,scm-apq8064", "qcom,scm";
283 clock-names = "core";
290 * That is why the ADC is referred to as "HKADC" - HouseKeeping
293 iio-hwmon {
294 compatible = "iio-hwmon";
295 io-channels = <&xoadc 0x00 0x01>, /* Battery */
305 #address-cells = <1>;
306 #size-cells = <1>;
308 compatible = "simple-bus";
311 compatible = "qcom,apq8064-pinctrl";
314 gpio-controller;
315 gpio-ranges = <&tlmm_pinmux 0 0 90>;
316 #gpio-cells = <2>;
317 interrupt-controller;
318 #interrupt-cells = <2>;
321 pinctrl-names = "default";
322 pinctrl-0 = <&ps_hold>;
330 intc: interrupt-controller@2000000 {
331 compatible = "qcom,msm-qgic2";
332 interrupt-controller;
333 #interrupt-cells = <3>;
339 compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer",
340 "qcom,msm-timer";
345 clock-frequency = <27000000>;
346 cpu-offset = <0x80000>;
349 acc0: clock-controller@2088000 {
350 compatible = "qcom,kpss-acc-v1";
353 clock-names = "pll8_vote", "pxo";
354 clock-output-names = "acpu0_aux";
355 #clock-cells = <0>;
358 acc1: clock-controller@2098000 {
359 compatible = "qcom,kpss-acc-v1";
362 clock-names = "pll8_vote", "pxo";
363 clock-output-names = "acpu1_aux";
364 #clock-cells = <0>;
367 acc2: clock-controller@20a8000 {
368 compatible = "qcom,kpss-acc-v1";
371 clock-names = "pll8_vote", "pxo";
372 clock-output-names = "acpu2_aux";
373 #clock-cells = <0>;
376 acc3: clock-controller@20b8000 {
377 compatible = "qcom,kpss-acc-v1";
380 clock-names = "pll8_vote", "pxo";
381 clock-output-names = "acpu3_aux";
382 #clock-cells = <0>;
385 saw0: power-controller@2089000 {
386 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
391 saw1: power-controller@2099000 {
392 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
397 saw2: power-controller@20a9000 {
398 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
403 saw3: power-controller@20b9000 {
404 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
409 sps_sic_non_secure: sps-sic-non-secure@12100000 {
416 compatible = "qcom,gsbi-v1.0.0";
417 cell-index = <1>;
420 clock-names = "iface";
421 #address-cells = <1>;
422 #size-cells = <1>;
425 syscon-tcsr = <&tcsr>;
428 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
433 clock-names = "core", "iface";
438 compatible = "qcom,i2c-qup-v1.1.1";
439 pinctrl-0 = <&i2c1_pins>;
440 pinctrl-1 = <&i2c1_pins_sleep>;
441 pinctrl-names = "default", "sleep";
445 clock-names = "core", "iface";
446 #address-cells = <1>;
447 #size-cells = <0>;
455 compatible = "qcom,gsbi-v1.0.0";
456 cell-index = <2>;
459 clock-names = "iface";
460 #address-cells = <1>;
461 #size-cells = <1>;
464 syscon-tcsr = <&tcsr>;
467 compatible = "qcom,i2c-qup-v1.1.1";
469 pinctrl-0 = <&i2c2_pins>;
470 pinctrl-1 = <&i2c2_pins_sleep>;
471 pinctrl-names = "default", "sleep";
474 clock-names = "core", "iface";
475 #address-cells = <1>;
476 #size-cells = <0>;
483 compatible = "qcom,gsbi-v1.0.0";
484 cell-index = <3>;
487 clock-names = "iface";
488 #address-cells = <1>;
489 #size-cells = <1>;
492 compatible = "qcom,i2c-qup-v1.1.1";
493 pinctrl-0 = <&i2c3_pins>;
494 pinctrl-1 = <&i2c3_pins_sleep>;
495 pinctrl-names = "default", "sleep";
500 clock-names = "core", "iface";
501 #address-cells = <1>;
502 #size-cells = <0>;
509 compatible = "qcom,gsbi-v1.0.0";
510 cell-index = <4>;
513 clock-names = "iface";
514 #address-cells = <1>;
515 #size-cells = <1>;
519 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
523 pinctrl-0 = <&gsbi4_uart_pin_a>;
524 pinctrl-names = "default";
526 clock-names = "core", "iface";
531 compatible = "qcom,i2c-qup-v1.1.1";
532 pinctrl-0 = <&i2c4_pins>;
533 pinctrl-1 = <&i2c4_pins_sleep>;
534 pinctrl-names = "default", "sleep";
539 clock-names = "core", "iface";
546 compatible = "qcom,gsbi-v1.0.0";
547 cell-index = <5>;
550 clock-names = "iface";
551 #address-cells = <1>;
552 #size-cells = <1>;
556 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
561 clock-names = "core", "iface";
566 compatible = "qcom,spi-qup-v1.1.1";
569 pinctrl-0 = <&spi5_default>;
570 pinctrl-1 = <&spi5_sleep>;
571 pinctrl-names = "default", "sleep";
573 clock-names = "core", "iface";
575 #address-cells = <1>;
576 #size-cells = <0>;
582 compatible = "qcom,gsbi-v1.0.0";
583 cell-index = <6>;
586 clock-names = "iface";
587 #address-cells = <1>;
588 #size-cells = <1>;
592 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
597 clock-names = "core", "iface";
602 compatible = "qcom,i2c-qup-v1.1.1";
603 pinctrl-0 = <&i2c6_pins>;
604 pinctrl-1 = <&i2c6_pins_sleep>;
605 pinctrl-names = "default", "sleep";
610 clock-names = "core", "iface";
617 compatible = "qcom,gsbi-v1.0.0";
618 cell-index = <7>;
621 clock-names = "iface";
622 #address-cells = <1>;
623 #size-cells = <1>;
625 syscon-tcsr = <&tcsr>;
628 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
633 clock-names = "core", "iface";
638 compatible = "qcom,i2c-qup-v1.1.1";
639 pinctrl-0 = <&i2c7_pins>;
640 pinctrl-1 = <&i2c7_pins_sleep>;
641 pinctrl-names = "default", "sleep";
646 clock-names = "core", "iface";
655 clock-names = "core";
661 qcom,controller-type = "pmic-arbiter";
665 interrupt-parent = <&tlmm_pinmux>;
667 #interrupt-cells = <2>;
668 interrupt-controller;
669 #address-cells = <1>;
670 #size-cells = <0>;
673 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
675 interrupt-controller;
676 #interrupt-cells = <2>;
677 gpio-controller;
678 #gpio-cells = <2>;
679 gpio-ranges = <&pm8821_mpps 0 0 4>;
687 qcom,controller-type = "pmic-arbiter";
691 interrupt-parent = <&tlmm_pinmux>;
693 #interrupt-cells = <2>;
694 interrupt-controller;
695 #address-cells = <1>;
696 #size-cells = <0>;
700 compatible = "qcom,pm8921-gpio",
701 "qcom,ssbi-gpio";
703 interrupt-controller;
704 #interrupt-cells = <2>;
705 gpio-controller;
706 gpio-ranges = <&pm8921_gpio 0 0 44>;
707 #gpio-cells = <2>;
712 compatible = "qcom,pm8921-mpp",
713 "qcom,ssbi-mpp";
715 gpio-controller;
716 #gpio-cells = <2>;
717 gpio-ranges = <&pm8921_mpps 0 0 12>;
718 interrupt-controller;
719 #interrupt-cells = <2>;
723 compatible = "qcom,pm8921-rtc";
724 interrupt-parent = <&pmicintc>;
727 allow-set-time;
731 compatible = "qcom,pm8921-pwrkey";
733 interrupt-parent = <&pmicintc>;
736 pull-up;
740 compatible = "qcom,pm8921-adc";
742 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
743 #address-cells = <2>;
744 #size-cells = <0>;
745 #io-channel-cells = <2>;
747 vcoin: adc-channel@0 {
750 vbat: adc-channel@1 {
753 dcin: adc-channel@2 {
756 vph_pwr: adc-channel@4 {
759 batt_therm: adc-channel@8 {
762 batt_id: adc-channel@9 {
765 usb_vbus: adc-channel@a {
768 die_temp: adc-channel@b {
771 ref_625mv: adc-channel@c {
774 ref_1250mv: adc-channel@d {
777 chg_temp: adc-channel@e {
780 ref_muxoff: adc-channel@f {
788 compatible = "qcom,apq8064-qfprom", "qcom,qfprom";
790 #address-cells = <1>;
791 #size-cells = <1>;
801 gcc: clock-controller@900000 {
802 compatible = "qcom,gcc-apq8064", "syscon";
804 #clock-cells = <1>;
805 #power-domain-cells = <1>;
806 #reset-cells = <1>;
810 clock-names = "cxo", "pxo", "pll4";
812 tsens: thermal-sensor {
813 compatible = "qcom,msm8960-tsens";
815 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
816 nvmem-cell-names = "calib", "calib_backup";
818 interrupt-names = "uplow";
821 #thermal-sensor-cells = <1>;
825 lcc: clock-controller@28000000 {
826 compatible = "qcom,lcc-apq8064";
828 #clock-cells = <1>;
829 #reset-cells = <1>;
836 clock-names = "pxo",
846 mmcc: clock-controller@4000000 {
847 compatible = "qcom,mmcc-apq8064";
849 #clock-cells = <1>;
850 #power-domain-cells = <1>;
851 #reset-cells = <1>;
860 clock-names = "pxo",
870 l2cc: clock-controller@2011000 {
871 compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon";
874 clock-names = "pll8_vote", "pxo";
875 #clock-cells = <0>;
879 compatible = "qcom,rpm-apq8064";
886 interrupt-names = "ack", "err", "wakeup";
888 rpmcc: clock-controller {
889 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
890 #clock-cells = <1>;
892 clock-names = "pxo", "cxo";
896 compatible = "qcom,rpm-pm8921-regulators";
940 pm8921_usb_switch: usb-switch {};
942 pm8921_hdmi_switch: hdmi-switch {
943 bias-pull-down;
951 compatible = "qcom,ci-hdrc";
956 clock-names = "core", "iface";
957 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
958 assigned-clock-rates = <60000000>;
960 reset-names = "core";
962 ahb-burst-config = <0>;
964 phy-names = "usb-phy";
966 #reset-cells = <1>;
970 compatible = "qcom,usb-hs-phy-apq8064",
971 "qcom,usb-hs-phy";
973 clock-names = "sleep", "ref";
975 reset-names = "por";
976 #phy-cells = <0>;
982 compatible = "qcom,ci-hdrc";
987 clock-names = "core", "iface";
988 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
989 assigned-clock-rates = <60000000>;
991 reset-names = "core";
993 ahb-burst-config = <0>;
995 phy-names = "usb-phy";
997 #reset-cells = <1>;
1001 compatible = "qcom,usb-hs-phy-apq8064",
1002 "qcom,usb-hs-phy";
1003 #phy-cells = <0>;
1005 clock-names = "sleep", "ref";
1007 reset-names = "por";
1013 compatible = "qcom,ci-hdrc";
1018 clock-names = "core", "iface";
1019 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
1020 assigned-clock-rates = <60000000>;
1022 reset-names = "core";
1024 ahb-burst-config = <0>;
1026 phy-names = "usb-phy";
1028 #reset-cells = <1>;
1032 compatible = "qcom,usb-hs-phy-apq8064",
1033 "qcom,usb-hs-phy";
1034 #phy-cells = <0>;
1036 clock-names = "sleep", "ref";
1038 reset-names = "por";
1044 compatible = "qcom,apq8064-sata-phy";
1047 reg-names = "phy_mem";
1049 clock-names = "cfg";
1050 #phy-cells = <0>;
1054 compatible = "qcom,apq8064-ahci", "generic-ahci";
1064 clock-names = "slave_iface",
1070 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1072 assigned-clock-rates = <100000000>, <100000000>;
1075 phy-names = "sata-phy";
1076 ports-implemented = <0x1>;
1081 arm,primecell-periphid = <0x00051180>;
1086 clock-names = "mclk", "apb_pclk";
1087 bus-width = <4>;
1088 cap-sd-highspeed;
1089 cap-mmc-highspeed;
1090 max-frequency = <192000000>;
1091 no-1-8-v;
1093 dma-names = "tx", "rx";
1096 sdcc3bam: dma-controller@12182000 {
1097 compatible = "qcom,bam-v1.3.0";
1101 clock-names = "bam_clk";
1102 #dma-cells = <1>;
1108 arm,primecell-periphid = <0x00051180>;
1113 clock-names = "mclk", "apb_pclk";
1114 bus-width = <4>;
1115 cap-sd-highspeed;
1116 cap-mmc-highspeed;
1117 max-frequency = <48000000>;
1119 dma-names = "tx", "rx";
1120 pinctrl-names = "default";
1121 pinctrl-0 = <&sdc4_gpios>;
1124 sdcc4bam: dma-controller@121c2000 {
1125 compatible = "qcom,bam-v1.3.0";
1129 clock-names = "bam_clk";
1130 #dma-cells = <1>;
1137 pinctrl-names = "default";
1138 pinctrl-0 = <&sdcc1_pins>;
1139 arm,primecell-periphid = <0x00051180>;
1143 clock-names = "mclk", "apb_pclk";
1144 bus-width = <8>;
1145 max-frequency = <96000000>;
1146 non-removable;
1147 cap-sd-highspeed;
1148 cap-mmc-highspeed;
1150 dma-names = "tx", "rx";
1153 sdcc1bam: dma-controller@12402000 {
1154 compatible = "qcom,bam-v1.3.0";
1158 clock-names = "bam_clk";
1159 #dma-cells = <1>;
1164 compatible = "qcom,tcsr-apq8064", "syscon";
1168 gpu: adreno-3xx@4300000 {
1169 compatible = "qcom,adreno-320.2", "qcom,adreno";
1171 reg-names = "kgsl_3d0_reg_memory";
1173 interrupt-names = "kgsl_3d0_irq";
1174 clock-names =
1250 operating-points-v2 = <&gpu_opp_table>;
1252 gpu_opp_table: opp-table {
1253 compatible = "operating-points-v2";
1255 opp-450000000 {
1256 opp-hz = /bits/ 64 <450000000>;
1259 opp-27000000 {
1260 opp-hz = /bits/ 64 <27000000>;
1271 compatible = "qcom,apq8064-dsi-ctrl",
1272 "qcom,mdss-dsi-ctrl";
1273 label = "MDSS DSI CTRL->0";
1274 #address-cells = <1>;
1275 #size-cells = <0>;
1278 reg-names = "dsi_ctrl";
1287 clock-names = "iface", "bus", "core_mmss",
1291 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1295 assigned-clock-parents = <&dsi0_phy 0>,
1299 syscon-sfpb = <&mmss_sfpb>;
1304 #address-cells = <1>;
1305 #size-cells = <0>;
1323 compatible = "qcom,dsi-phy-28nm-8960";
1324 #clock-cells = <1>;
1325 #phy-cells = <0>;
1330 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1331 clock-names = "iface", "ref";
1338 compatible = "qcom,mdss-dsi-ctrl";
1341 reg-names = "dsi_ctrl";
1350 clock-names = "iface",
1358 assigned-clocks = <&mmcc DSI2_BYTE_SRC>,
1362 assigned-clock-parents = <&dsi1_phy 0>,
1367 syscon-sfpb = <&mmss_sfpb>;
1370 #address-cells = <1>;
1371 #size-cells = <0>;
1376 #address-cells = <1>;
1377 #size-cells = <0>;
1394 dsi1_phy: dsi-phy@5800200 {
1395 compatible = "qcom,dsi-phy-28nm-8960";
1399 reg-names = "dsi_pll",
1402 clock-names = "iface",
1406 #clock-cells = <1>;
1407 #phy-cells = <0>;
1413 compatible = "qcom,apq8064-iommu";
1414 #iommu-cells = <1>;
1415 clock-names =
1429 compatible = "qcom,apq8064-iommu";
1430 #iommu-cells = <1>;
1431 clock-names =
1445 compatible = "qcom,apq8064-iommu";
1446 #iommu-cells = <1>;
1447 clock-names =
1461 compatible = "qcom,apq8064-iommu";
1462 #iommu-cells = <1>;
1463 clock-names =
1477 compatible = "qcom,pcie-apq8064";
1482 reg-names = "dbi", "elbi", "parf", "config";
1484 linux,pci-domain = <0>;
1485 bus-range = <0x00 0xff>;
1486 num-lanes = <1>;
1487 #address-cells = <3>;
1488 #size-cells = <2>;
1492 interrupt-names = "msi";
1493 #interrupt-cells = <1>;
1494 interrupt-map-mask = <0 0 0 0x7>;
1495 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1502 clock-names = "core", "iface", "phy";
1508 reset-names = "axi", "ahb", "por", "pci", "phy";
1512 hdmi: hdmi-tx@4a00000 {
1513 compatible = "qcom,hdmi-tx-8960";
1514 pinctrl-names = "default";
1515 pinctrl-0 = <&hdmi_pinctrl>;
1517 reg-names = "core_physical";
1522 clock-names = "core",
1531 #address-cells = <1>;
1532 #size-cells = <0>;
1549 compatible = "qcom,hdmi-phy-8960";
1552 reg-names = "hdmi_phy",
1556 clock-names = "slave_iface";
1557 #phy-cells = <0>;
1558 #clock-cells = <0>;
1563 mdp: display-controller@5100000 {
1573 clock-names = "core_clk",
1586 #address-cells = <1>;
1587 #size-cells = <0>;
1615 riva: riva-pil@3200800 {
1616 compatible = "qcom,riva-pil";
1619 reg-names = "ccu", "dxe", "pmu";
1621 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1623 interrupt-names = "wdog", "fatal";
1625 memory-region = <&wcnss_mem>;
1627 vddcx-supply = <&pm8921_s3>;
1628 vddmx-supply = <&pm8921_l24>;
1629 vddpx-supply = <&pm8921_s4>;
1637 clock-names = "xo";
1639 vddxo-supply = <&pm8921_l4>;
1640 vddrfa-supply = <&pm8921_s2>;
1641 vddpa-supply = <&pm8921_l10>;
1642 vdddig-supply = <&pm8921_lvs2>;
1645 smd-edge {
1649 qcom,smd-edge = <6>;
1655 qcom,smd-channels = "WCNSS_CTRL";
1660 compatible = "qcom,wcnss-bt";
1664 compatible = "qcom,wcnss-wlan";
1668 interrupt-names = "tx", "rx";
1670 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1671 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1678 compatible = "arm,coresight-etb10", "arm,primecell";
1682 clock-names = "apb_pclk";
1684 in-ports {
1687 remote-endpoint = <&replicator_out0>;
1694 compatible = "arm,coresight-tpiu", "arm,primecell";
1698 clock-names = "apb_pclk";
1700 in-ports {
1703 remote-endpoint = <&replicator_out1>;
1710 compatible = "arm,coresight-static-replicator";
1713 clock-names = "apb_pclk";
1715 out-ports {
1716 #address-cells = <1>;
1717 #size-cells = <0>;
1722 remote-endpoint = <&etb_in>;
1728 remote-endpoint = <&tpiu_in>;
1733 in-ports {
1736 remote-endpoint = <&funnel_out>;
1743 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1747 clock-names = "apb_pclk";
1749 in-ports {
1750 #address-cells = <1>;
1751 #size-cells = <0>;
1755 * 2 - connected to STM component
1756 * 3 - not-connected
1757 * 6 - not-connected
1758 * 7 - not-connected
1763 remote-endpoint = <&etm0_out>;
1769 remote-endpoint = <&etm1_out>;
1775 remote-endpoint = <&etm2_out>;
1781 remote-endpoint = <&etm3_out>;
1786 out-ports {
1789 remote-endpoint = <&replicator_in>;
1796 compatible = "arm,coresight-etm3x", "arm,primecell";
1800 clock-names = "apb_pclk";
1804 out-ports {
1807 remote-endpoint = <&funnel_in0>;
1814 compatible = "arm,coresight-etm3x", "arm,primecell";
1818 clock-names = "apb_pclk";
1822 out-ports {
1825 remote-endpoint = <&funnel_in1>;
1832 compatible = "arm,coresight-etm3x", "arm,primecell";
1836 clock-names = "apb_pclk";
1840 out-ports {
1843 remote-endpoint = <&funnel_in4>;
1850 compatible = "arm,coresight-etm3x", "arm,primecell";
1854 clock-names = "apb_pclk";
1858 out-ports {
1861 remote-endpoint = <&funnel_in5>;
1868 #include "qcom-apq8064-pins.dtsi"