dts/qcom/qcom-apq8064.dtsi

13 	#address-cells = <1>;
14 	#size-cells = <1>;
20 		#address-cells = <1>;
21 		#size-cells = <1>;
36 		#address-cells = <1>;
50 		CPU1: cpu@1 {
54 			reg = <1>;
193 		interrupts = <1 10 0x304>;
219 		#hwlock-cells = <1>;
232 		#address-cells = <1>;
235 		qcom,ipc-1 = <&l2cc 8 4>;
242 			#qcom,smem-state-cells = <1>;
245 		modem_smsm: modem@1 {
246 			reg = <1>;
305 		#address-cells = <1>;
306 		#size-cells = <1>;
341 			interrupts = <1 1 0x301>,
342 				     <1 2 0x301>,
343 				     <1 3 0x301>;
386 			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
392 			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
398 			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
404 			compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
417 			cell-index = <1>;
421 			#address-cells = <1>;
422 			#size-cells = <1>;
440 				pinctrl-1 = <&i2c1_pins_sleep>;
446 				#address-cells = <1>;
460 			#address-cells = <1>;
461 			#size-cells = <1>;
470 				pinctrl-1 = <&i2c2_pins_sleep>;
475 				#address-cells = <1>;
488 			#address-cells = <1>;
489 			#size-cells = <1>;
494 				pinctrl-1 = <&i2c3_pins_sleep>;
501 				#address-cells = <1>;
514 			#address-cells = <1>;
515 			#size-cells = <1>;
533 				pinctrl-1 = <&i2c4_pins_sleep>;
544 		gsbi5: gsbi@1a200000 {
551 			#address-cells = <1>;
552 			#size-cells = <1>;
555 			gsbi5_serial: serial@1a240000 {
565 			gsbi5_spi: spi@1a280000 {
570 				pinctrl-1 = <&spi5_sleep>;
575 				#address-cells = <1>;
587 			#address-cells = <1>;
588 			#size-cells = <1>;
604 				pinctrl-1 = <&i2c6_pins_sleep>;
622 			#address-cells = <1>;
623 			#size-cells = <1>;
640 				pinctrl-1 = <&i2c7_pins_sleep>;
651 		rng@1a500000 {
669 				#address-cells = <1>;
695 				#address-cells = <1>;
725 					interrupts = <39 1>;
730 				pwrkey@1c {
734 					interrupts = <50 1>, <51 1>;
750 					vbat: adc-channel@1 {
790 			#address-cells = <1>;
791 			#size-cells = <1>;
804 			#clock-cells = <1>;
805 			#power-domain-cells = <1>;
806 			#reset-cells = <1>;
821 				#thermal-sensor-cells = <1>;
828 			#clock-cells = <1>;
829 			#reset-cells = <1>;
849 			#clock-cells = <1>;
850 			#power-domain-cells = <1>;
851 			#reset-cells = <1>;
855 				 <&dsi0_phy 1>,
857 				 <&dsi1_phy 1>,
890 				#clock-cells = <1>;
966 			#reset-cells = <1>;
997 			#reset-cells = <1>;
1028 			#reset-cells = <1>;
1043 		sata_phy0: phy@1b400000 {
1091 			no-1-8-v;
1092 			dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1102 			#dma-cells = <1>;
1118 			dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1130 			#dma-cells = <1>;
1149 			dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1159 			#dma-cells = <1>;
1163 		tcsr: syscon@1a400000 {
1186 				  &gfx3d 1
1218 				  &gfx3d1 1
1274 			#address-cells = <1>;
1297 						<&dsi0_phy 1>,
1298 						<&dsi0_phy 1>;
1304 				#address-cells = <1>;
1313 				port@1 {
1314 					reg = <1>;
1324 			#clock-cells = <1>;
1364 						 <&dsi1_phy 1>,
1365 						 <&dsi1_phy 1>;
1370 			#address-cells = <1>;
1376 				#address-cells = <1>;
1385 				port@1 {
1386 					reg = <1>;
1406 			#clock-cells = <1>;
1414 			#iommu-cells = <1>;
1430 			#iommu-cells = <1>;
1446 			#iommu-cells = <1>;
1462 			#iommu-cells = <1>;
1476 		pcie: pci@1b500000 {
1486 			num-lanes = <1>;
1493 			#interrupt-cells = <1>;
1495 			interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1531 				#address-cells = <1>;
1540 				port@1 {
1541 					reg = <1>;
1586 				#address-cells = <1>;
1595 				port@1 {
1596 					reg = <1>;
1677 		etb@1a01000 {
1693 		tpiu@1a03000 {
1716 				#address-cells = <1>;
1725 				port@1 {
1726 					reg = <1>;
1742 		funnel@1a04000 {
1750 				#address-cells = <1>;
1766 				port@1 {
1767 					reg = <1>;
1795 		etm@1a1c000 {
1813 		etm@1a1d000 {
1831 		etm@1a1e000 {
1849 		etm@1a1f000 {