Lines Matching +full:1 +full:a01000
10 #address-cells = <1>;
11 #size-cells = <1>;
50 #address-cells = <1>;
109 #address-cells = <1>;
110 #size-cells = <1>;
119 #address-cells = <1>;
120 #size-cells = <1>;
124 intc: interrupt-controller@a01000 {
145 #address-cells = <1>;
146 #size-cells = <1>;
152 #address-cells = <1>;
153 #size-cells = <1>;
179 #address-cells = <1>;
191 #address-cells = <1>;
203 #address-cells = <1>;
215 #address-cells = <1>;
274 dmas = <&sdma 37 1 0>,
275 <&sdma 38 1 0>;
290 dmas = <&sdma 41 1 0>,
291 <&sdma 42 1 0>;
306 dmas = <&sdma 45 1 0>,
307 <&sdma 46 1 0>;
398 gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
399 <&iomuxc 3 23 1>, <&iomuxc 4 25 1>,
400 <&iomuxc 5 24 1>, <&iomuxc 6 19 1>,
403 <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
417 <&iomuxc 11 56 1>, <&iomuxc 12 61 3>,
418 <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
419 <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
420 <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
436 <&iomuxc 23 136 1>, <&iomuxc 24 91 1>,
437 <&iomuxc 25 99 1>, <&iomuxc 26 92 1>,
438 <&iomuxc 27 100 1>, <&iomuxc 28 93 1>,
439 <&iomuxc 29 101 1>, <&iomuxc 30 94 1>,
440 <&iomuxc 31 102 1>;
452 gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
453 <&iomuxc 2 96 1>, <&iomuxc 3 104 1>,
454 <&iomuxc 4 97 1>, <&iomuxc 5 105 1>,
455 <&iomuxc 6 98 1>, <&iomuxc 7 106 1>,
456 <&iomuxc 8 28 1>, <&iomuxc 9 27 1>,
457 <&iomuxc 10 26 1>, <&iomuxc 11 29 1>,
458 <&iomuxc 12 32 1>, <&iomuxc 13 31 1>,
459 <&iomuxc 14 30 1>, <&iomuxc 15 33 1>,
460 <&iomuxc 16 84 1>, <&iomuxc 17 79 2>,
461 <&iomuxc 19 78 1>, <&iomuxc 20 76 1>,
462 <&iomuxc 21 81 2>, <&iomuxc 23 75 1>,
463 <&iomuxc 24 83 1>, <&iomuxc 25 74 1>,
464 <&iomuxc 26 77 1>, <&iomuxc 27 159 1>,
465 <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
466 <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
478 gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
479 <&iomuxc 2 155 1>, <&iomuxc 3 153 1>,
480 <&iomuxc 4 150 1>, <&iomuxc 5 149 1>,
481 <&iomuxc 6 144 1>, <&iomuxc 7 147 1>,
482 <&iomuxc 8 142 1>, <&iomuxc 9 146 1>,
483 <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
484 <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
485 <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
486 <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
487 <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
488 <&iomuxc 21 161 1>;
519 #clock-cells = <1>;
531 reg_vdd1p1: regulator-1p1 {
588 anatop-min-bit-val = <1>;
604 anatop-min-bit-val = <1>;
621 anatop-min-bit-val = <1>;
690 #reset-cells = <1>;
704 #address-cells = <1>;
712 pd_pu: power-domain@1 {
713 reg = <1>;
798 #address-cells = <1>;
799 #size-cells = <1>;
822 fsl,usbmisc = <&usbmisc 1>;
845 #index-cells = <1>;
910 #address-cells = <1>;
920 #address-cells = <1>;
930 #address-cells = <1>;
954 #size-cells = <1>;
965 #address-cells = <1>;
966 #size-cells = <1>;