nxp/imx/imx6qp.dtsi

1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 			compatible = "mmio-sram";
13 			#address-cells = <1>;
14 			#size-cells = <1>;
15 			clocks = <&clks IMX6QDL_CLK_OCRAM>;
19 			compatible = "mmio-sram";
22 			#address-cells = <1>;
23 			#size-cells = <1>;
24 			clocks = <&clks IMX6QDL_CLK_OCRAM>;
28 			pre1: pre@21c8000 {
29 				compatible = "fsl,imx6qp-pre";
32 				clocks = <&clks IMX6QDL_CLK_PRE0>;
33 				clock-names = "axi";
37 			pre2: pre@21c9000 {
38 				compatible = "fsl,imx6qp-pre";
41 				clocks = <&clks IMX6QDL_CLK_PRE1>;
42 				clock-names = "axi";
46 			pre3: pre@21ca000 {
47 				compatible = "fsl,imx6qp-pre";
50 				clocks = <&clks IMX6QDL_CLK_PRE2>;
51 				clock-names = "axi";
55 			pre4: pre@21cb000 {
56 				compatible = "fsl,imx6qp-pre";
59 				clocks = <&clks IMX6QDL_CLK_PRE3>;
60 				clock-names = "axi";
65 				compatible = "fsl,imx6qp-prg";
67 				clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
69 				clock-names = "ipg", "axi";
74 				compatible = "fsl,imx6qp-prg";
76 				clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
78 				clock-names = "ipg", "axi";
91 	compatible = "fsl,imx6qp-gpc", "fsl,imx6q-gpc";
95 	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
100 	compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu";
105 	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
109 	clock-names = "di0_pll", "di1_pll",
115 	compatible = "fsl,imx6qp-mmdc", "fsl,imx6q-mmdc";
119 	compatible = "fsl,imx6qp-pcie";