Lines Matching +full:speed +full:- +full:grade
1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 * pre-existing /chosen node to be available to insert the
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <0>;
70 compatible = "fixed-clock";
71 #clock-cells = <0>;
72 clock-frequency = <24000000>;
77 #address-cells = <1>;
78 #size-cells = <0>;
79 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
83 lvds-channel@0 {
84 #address-cells = <1>;
85 #size-cells = <0>;
93 remote-endpoint = <&ipu1_di0_lvds0>;
101 remote-endpoint = <&ipu1_di1_lvds0>;
106 lvds-channel@1 {
107 #address-cells = <1>;
108 #size-cells = <0>;
116 remote-endpoint = <&ipu1_di0_lvds1>;
124 remote-endpoint = <&ipu1_di1_lvds1>;
131 compatible = "arm,cortex-a9-pmu";
132 interrupt-parent = <&gpc>;
137 compatible = "usb-nop-xceiv";
138 #phy-cells = <0>;
142 compatible = "usb-nop-xceiv";
143 #phy-cells = <0>;
147 #address-cells = <1>;
148 #size-cells = <1>;
149 compatible = "simple-bus";
150 interrupt-parent = <&gpc>;
153 dma_apbh: dma-controller@110000 {
154 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
160 #dma-cells = <1>;
161 dma-channels = <4>;
165 gpmi: nand-controller@112000 {
166 compatible = "fsl,imx6q-gpmi-nand";
168 reg-names = "gpmi-nand", "bch";
170 interrupt-names = "bch";
176 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
179 dma-names = "rx-tx";
189 clock-names = "iahb", "isfr";
193 #address-cells = <1>;
194 #size-cells = <0>;
200 remote-endpoint = <&ipu1_di0_hdmi>;
208 remote-endpoint = <&ipu1_di1_hdmi>;
221 clock-names = "bus", "core", "shader";
222 power-domains = <&pd_pu>;
223 #cooling-cells = <2>;
232 clock-names = "bus", "core";
233 power-domains = <&pd_pu>;
234 #cooling-cells = <2>;
238 compatible = "arm,cortex-a9-twd-timer";
241 interrupt-parent = <&intc>;
245 intc: interrupt-controller@a01000 {
246 compatible = "arm,cortex-a9-gic";
247 #interrupt-cells = <3>;
248 interrupt-controller;
251 interrupt-parent = <&intc>;
254 L2: cache-controller@a02000 {
255 compatible = "arm,pl310-cache";
258 cache-unified;
259 cache-level = <2>;
260 arm,tag-latency = <4 2 3>;
261 arm,data-latency = <4 2 3>;
262 arm,shared-override;
266 compatible = "fsl,imx6q-pcie";
269 reg-names = "dbi", "config";
270 #address-cells = <3>;
271 #size-cells = <2>;
273 bus-range = <0x00 0xff>;
275 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
276 num-lanes = <1>;
278 interrupt-names = "msi";
279 #interrupt-cells = <1>;
280 interrupt-map-mask = <0 0 0 0x7>;
281 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
288 clock-names = "pcie", "pcie_bus", "pcie_phy";
293 compatible = "fsl,aips-bus", "simple-bus";
294 #address-cells = <1>;
295 #size-cells = <1>;
299 spba-bus@2000000 {
300 compatible = "fsl,spba-bus", "simple-bus";
301 #address-cells = <1>;
302 #size-cells = <1>;
307 compatible = "fsl,imx35-spdif";
312 dma-names = "rx", "tx";
318 clock-names = "core", "rxtx0",
327 #address-cells = <1>;
328 #size-cells = <0>;
329 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
334 clock-names = "ipg", "per";
336 dma-names = "rx", "tx";
341 #address-cells = <1>;
342 #size-cells = <0>;
343 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
348 clock-names = "ipg", "per";
350 dma-names = "rx", "tx";
355 #address-cells = <1>;
356 #size-cells = <0>;
357 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
362 clock-names = "ipg", "per";
364 dma-names = "rx", "tx";
369 #address-cells = <1>;
370 #size-cells = <0>;
371 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
376 clock-names = "ipg", "per";
378 dma-names = "rx", "tx";
383 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
388 clock-names = "ipg", "per";
390 dma-names = "rx", "tx";
395 #sound-dai-cells = <0>;
396 compatible = "fsl,imx35-esai";
404 clock-names = "core", "mem", "extal", "fsys", "spba";
406 dma-names = "rx", "tx";
411 #sound-dai-cells = <0>;
412 compatible = "fsl,imx6q-ssi",
413 "fsl,imx51-ssi";
418 clock-names = "ipg", "baud";
421 dma-names = "rx", "tx";
422 fsl,fifo-depth = <15>;
427 #sound-dai-cells = <0>;
428 compatible = "fsl,imx6q-ssi",
429 "fsl,imx51-ssi";
434 clock-names = "ipg", "baud";
437 dma-names = "rx", "tx";
438 fsl,fifo-depth = <15>;
443 #sound-dai-cells = <0>;
444 compatible = "fsl,imx6q-ssi",
445 "fsl,imx51-ssi";
450 clock-names = "ipg", "baud";
453 dma-names = "rx", "tx";
454 fsl,fifo-depth = <15>;
459 compatible = "fsl,imx53-asrc";
469 clock-names = "mem", "ipg", "asrck_0",
476 dma-names = "rxa", "rxb", "rxc",
478 fsl,asrc-rate = <48000>;
479 fsl,asrc-width = <16>;
483 spba-bus@203c000 {
493 interrupt-names = "bit", "jpeg";
496 clock-names = "per", "ahb";
497 power-domains = <&pd_pu>;
507 #pwm-cells = <3>;
508 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
513 clock-names = "ipg", "per";
518 #pwm-cells = <3>;
519 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
524 clock-names = "ipg", "per";
529 #pwm-cells = <3>;
530 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
535 clock-names = "ipg", "per";
540 #pwm-cells = <3>;
541 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
546 clock-names = "ipg", "per";
551 compatible = "fsl,imx6q-flexcan";
556 clock-names = "ipg", "per";
557 fsl,stop-mode = <&gpr 0x34 28>;
562 compatible = "fsl,imx6q-flexcan";
567 clock-names = "ipg", "per";
568 fsl,stop-mode = <&gpr 0x34 29>;
573 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
579 clock-names = "ipg", "per", "osc_per";
583 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
587 gpio-controller;
588 #gpio-cells = <2>;
589 interrupt-controller;
590 #interrupt-cells = <2>;
594 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
598 gpio-controller;
599 #gpio-cells = <2>;
600 interrupt-controller;
601 #interrupt-cells = <2>;
605 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
609 gpio-controller;
610 #gpio-cells = <2>;
611 interrupt-controller;
612 #interrupt-cells = <2>;
616 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
620 gpio-controller;
621 #gpio-cells = <2>;
622 interrupt-controller;
623 #interrupt-cells = <2>;
627 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
631 gpio-controller;
632 #gpio-cells = <2>;
633 interrupt-controller;
634 #interrupt-cells = <2>;
638 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
642 gpio-controller;
643 #gpio-cells = <2>;
644 interrupt-controller;
645 #interrupt-cells = <2>;
649 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
653 gpio-controller;
654 #gpio-cells = <2>;
655 interrupt-controller;
656 #interrupt-cells = <2>;
660 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
668 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
675 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
682 clks: clock-controller@20c4000 {
683 compatible = "fsl,imx6q-ccm";
687 #clock-cells = <1>;
691 compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd";
697 reg_vdd1p1: regulator-1p1 {
698 compatible = "fsl,anatop-regulator";
699 regulator-name = "vdd1p1";
700 regulator-min-microvolt = <1000000>;
701 regulator-max-microvolt = <1200000>;
702 regulator-always-on;
703 anatop-reg-offset = <0x110>;
704 anatop-vol-bit-shift = <8>;
705 anatop-vol-bit-width = <5>;
706 anatop-min-bit-val = <4>;
707 anatop-min-voltage = <800000>;
708 anatop-max-voltage = <1375000>;
709 anatop-enable-bit = <0>;
712 reg_vdd3p0: regulator-3p0 {
713 compatible = "fsl,anatop-regulator";
714 regulator-name = "vdd3p0";
715 regulator-min-microvolt = <2800000>;
716 regulator-max-microvolt = <3150000>;
717 regulator-always-on;
718 anatop-reg-offset = <0x120>;
719 anatop-vol-bit-shift = <8>;
720 anatop-vol-bit-width = <5>;
721 anatop-min-bit-val = <0>;
722 anatop-min-voltage = <2625000>;
723 anatop-max-voltage = <3400000>;
724 anatop-enable-bit = <0>;
727 reg_vdd2p5: regulator-2p5 {
728 compatible = "fsl,anatop-regulator";
729 regulator-name = "vdd2p5";
730 regulator-min-microvolt = <2250000>;
731 regulator-max-microvolt = <2750000>;
732 regulator-always-on;
733 anatop-reg-offset = <0x130>;
734 anatop-vol-bit-shift = <8>;
735 anatop-vol-bit-width = <5>;
736 anatop-min-bit-val = <0>;
737 anatop-min-voltage = <2100000>;
738 anatop-max-voltage = <2875000>;
739 anatop-enable-bit = <0>;
742 reg_arm: regulator-vddcore {
743 compatible = "fsl,anatop-regulator";
744 regulator-name = "vddarm";
745 regulator-min-microvolt = <725000>;
746 regulator-max-microvolt = <1450000>;
747 regulator-always-on;
748 anatop-reg-offset = <0x140>;
749 anatop-vol-bit-shift = <0>;
750 anatop-vol-bit-width = <5>;
751 anatop-delay-reg-offset = <0x170>;
752 anatop-delay-bit-shift = <24>;
753 anatop-delay-bit-width = <2>;
754 anatop-min-bit-val = <1>;
755 anatop-min-voltage = <725000>;
756 anatop-max-voltage = <1450000>;
759 reg_pu: regulator-vddpu {
760 compatible = "fsl,anatop-regulator";
761 regulator-name = "vddpu";
762 regulator-min-microvolt = <725000>;
763 regulator-max-microvolt = <1450000>;
764 regulator-enable-ramp-delay = <380>;
765 anatop-reg-offset = <0x140>;
766 anatop-vol-bit-shift = <9>;
767 anatop-vol-bit-width = <5>;
768 anatop-delay-reg-offset = <0x170>;
769 anatop-delay-bit-shift = <26>;
770 anatop-delay-bit-width = <2>;
771 anatop-min-bit-val = <1>;
772 anatop-min-voltage = <725000>;
773 anatop-max-voltage = <1450000>;
776 reg_soc: regulator-vddsoc {
777 compatible = "fsl,anatop-regulator";
778 regulator-name = "vddsoc";
779 regulator-min-microvolt = <725000>;
780 regulator-max-microvolt = <1450000>;
781 regulator-always-on;
782 anatop-reg-offset = <0x140>;
783 anatop-vol-bit-shift = <18>;
784 anatop-vol-bit-width = <5>;
785 anatop-delay-reg-offset = <0x170>;
786 anatop-delay-bit-shift = <28>;
787 anatop-delay-bit-width = <2>;
788 anatop-min-bit-val = <1>;
789 anatop-min-voltage = <725000>;
790 anatop-max-voltage = <1450000>;
794 compatible = "fsl,imx6q-tempmon";
795 interrupt-parent = <&gpc>;
798 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
799 nvmem-cell-names = "calib", "temp_grade";
801 #thermal-sensor-cells = <0>;
806 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
814 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
822 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
825 snvs_rtc: snvs-rtc-lp {
826 compatible = "fsl,sec-v4.0-mon-rtc-lp";
833 snvs_poweroff: snvs-poweroff {
834 compatible = "syscon-poweroff";
842 snvs_pwrkey: snvs-powerkey {
843 compatible = "fsl,sec-v4.0-pwrkey";
847 wakeup-source;
851 snvs_lpgpr: snvs-lpgpr {
852 compatible = "fsl,imx6q-snvs-lpgpr";
866 src: reset-controller@20d8000 {
867 compatible = "fsl,imx6q-src", "fsl,imx51-src";
871 #reset-cells = <1>;
875 compatible = "fsl,imx6q-gpc";
877 interrupt-controller;
878 #interrupt-cells = <3>;
880 interrupt-parent = <&intc>;
882 clock-names = "ipg";
885 #address-cells = <1>;
886 #size-cells = <0>;
888 power-domain@0 {
890 #power-domain-cells = <0>;
892 pd_pu: power-domain@1 {
894 #power-domain-cells = <0>;
895 power-supply = <®_pu>;
906 gpr: iomuxc-gpr@20e0000 {
907 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
910 mux: mux-controller {
911 compatible = "mmio-mux";
912 #mux-control-cells = <1>;
917 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
931 sdma: dma-controller@20ec000 {
932 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
937 clock-names = "ipg", "ahb";
938 #dma-cells = <3>;
939 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
944 compatible = "fsl,aips-bus", "simple-bus";
945 #address-cells = <1>;
946 #size-cells = <1>;
951 compatible = "fsl,sec-v4.0";
952 #address-cells = <1>;
953 #size-cells = <1>;
960 clock-names = "mem", "aclk", "ipg", "emi_slow";
963 compatible = "fsl,sec-v4.0-job-ring";
969 compatible = "fsl,sec-v4.0-job-ring";
980 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
986 ahb-burst-config = <0x0>;
987 tx-burst-size-dword = <0x10>;
988 rx-burst-size-dword = <0x10>;
993 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1000 ahb-burst-config = <0x0>;
1001 tx-burst-size-dword = <0x10>;
1002 rx-burst-size-dword = <0x10>;
1007 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1015 ahb-burst-config = <0x0>;
1016 tx-burst-size-dword = <0x10>;
1017 rx-burst-size-dword = <0x10>;
1022 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1030 ahb-burst-config = <0x0>;
1031 tx-burst-size-dword = <0x10>;
1032 rx-burst-size-dword = <0x10>;
1037 #index-cells = <1>;
1038 compatible = "fsl,imx6q-usbmisc";
1044 compatible = "fsl,imx6q-fec";
1046 interrupt-names = "int0", "pps";
1053 clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
1054 fsl,stop-mode = <&gpr 0x34 27>;
1055 nvmem-cells = <&fec_mac_addr>;
1056 nvmem-cell-names = "mac-address";
1068 compatible = "fsl,imx6q-usdhc";
1074 clock-names = "ipg", "ahb", "per";
1075 bus-width = <4>;
1080 compatible = "fsl,imx6q-usdhc";
1086 clock-names = "ipg", "ahb", "per";
1087 bus-width = <4>;
1092 compatible = "fsl,imx6q-usdhc";
1098 clock-names = "ipg", "ahb", "per";
1099 bus-width = <4>;
1104 compatible = "fsl,imx6q-usdhc";
1110 clock-names = "ipg", "ahb", "per";
1111 bus-width = <4>;
1116 #address-cells = <1>;
1117 #size-cells = <0>;
1118 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1126 #address-cells = <1>;
1127 #size-cells = <0>;
1128 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1138 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1149 mmdc0: memory-controller@21b0000 { /* MMDC0 */
1150 compatible = "fsl,imx6q-mmdc";
1155 mmdc1: memory-controller@21b4000 { /* MMDC1 */
1156 compatible = "fsl,imx6q-mmdc";
1162 #address-cells = <2>;
1163 #size-cells = <1>;
1164 compatible = "fsl,imx6q-weim";
1168 fsl,weim-cs-gpr = <&gpr>;
1173 compatible = "fsl,imx6q-ocotp", "syscon";
1176 #address-cells = <1>;
1177 #size-cells = <1>;
1179 cpu_speed_grade: speed-grade@10 {
1187 tempmon_temp_grade: temp-grade@20 {
1191 fec_mac_addr: mac-addr@88 {
1207 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1213 compatible = "fsl,imx6-mipi-csi2";
1215 #address-cells = <1>;
1216 #size-cells = <0>;
1221 clock-names = "dphy", "ref", "pix";
1230 #address-cells = <1>;
1231 #size-cells = <0>;
1237 remote-endpoint = <&ipu1_di0_mipi>;
1245 remote-endpoint = <&ipu1_di1_mipi>;
1252 compatible = "fsl,imx6q-vdoa";
1259 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1264 clock-names = "ipg", "per";
1266 dma-names = "rx", "tx";
1271 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1276 clock-names = "ipg", "per";
1278 dma-names = "rx", "tx";
1283 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1288 clock-names = "ipg", "per";
1290 dma-names = "rx", "tx";
1295 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1300 clock-names = "ipg", "per";
1302 dma-names = "rx", "tx";
1308 #address-cells = <1>;
1309 #size-cells = <0>;
1310 compatible = "fsl,imx6q-ipu";
1317 clock-names = "bus", "di0", "di1";
1324 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1333 #address-cells = <1>;
1334 #size-cells = <0>;
1343 remote-endpoint = <&hdmi_mux_0>;
1348 remote-endpoint = <&mipi_mux_0>;
1353 remote-endpoint = <&lvds0_mux_0>;
1358 remote-endpoint = <&lvds1_mux_0>;
1363 #address-cells = <1>;
1364 #size-cells = <0>;
1373 remote-endpoint = <&hdmi_mux_1>;
1378 remote-endpoint = <&mipi_mux_1>;
1383 remote-endpoint = <&lvds0_mux_1>;
1388 remote-endpoint = <&lvds1_mux_1>;