Lines Matching +full:0 +full:xf0c88080
19 fsl,pcr = <0xf0c88080>; /* non-standard but required */
36 reg_3v3: regulator-0 {
52 pinctrl-0 = <&pinctrl_i2c1>;
57 reg = <0x51>;
63 reg = <0x64>;
71 MX27_PAD_I2C_DATA__I2C_DATA 0x0
72 MX27_PAD_I2C_CLK__I2C_CLK 0x0
78 MX27_PAD_RTCK__OWIRE 0x0
84 MX27_PAD_SD2_CLK__SD2_CLK 0x0
85 MX27_PAD_SD2_CMD__SD2_CMD 0x0
86 MX27_PAD_SD2_D0__SD2_D0 0x0
87 MX27_PAD_SD2_D1__SD2_D1 0x0
88 MX27_PAD_SD2_D2__SD2_D2 0x0
89 MX27_PAD_SD2_D3__SD2_D3 0x0
90 MX27_PAD_SSI3_RXDAT__GPIO3_29 0x0 /* CD */
96 MX27_PAD_UART1_TXD__UART1_TXD 0x0
97 MX27_PAD_UART1_RXD__UART1_RXD 0x0
98 MX27_PAD_UART1_CTS__UART1_CTS 0x0
99 MX27_PAD_UART1_RTS__UART1_RTS 0x0
105 MX27_PAD_UART2_TXD__UART2_TXD 0x0
106 MX27_PAD_UART2_RXD__UART2_RXD 0x0
107 MX27_PAD_UART2_CTS__UART2_CTS 0x0
108 MX27_PAD_UART2_RTS__UART2_RTS 0x0
114 MX27_PAD_UART3_TXD__UART3_TXD 0x0
115 MX27_PAD_UART3_RXD__UART3_RXD 0x0
116 MX27_PAD_UART3_CTS__UART3_CTS 0x0
117 MX27_PAD_UART3_RTS__UART3_RTS 0x0
125 pinctrl-0 = <&pinctrl_owire1>;
131 pinctrl-0 = <&pinctrl_sdhc2>;
139 pinctrl-0 = <&pinctrl_uart1>;
146 pinctrl-0 = <&pinctrl_uart2>;
153 pinctrl-0 = <&pinctrl_uart3>;