dts/marvell/armada-388-clearfog.dts

1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include "armada-388-clearfog.dtsi"
13 	compatible = "solidrun,clearfog-a1", "marvell,armada388",
17 		internal-regs {
27 				reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
33 	gpio-keys {
34 		compatible = "gpio-keys";
35 		pinctrl-0 = <&rear_button_pins>;
36 		pinctrl-names = "default";
38 		button-0 {
41 			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
42 			linux,can-disable;
50 	phy-mode = "1000base-x";
52 	fixed-link {
54 		full-duplex;
61 	 *  0-CON3 CLKREQ#
62 	 *  1-CON3 PERST#
63 	 *  2-CON2 PERST#
64 	 *  3-CON3 W_DISABLE
65 	 *  4-CON2 CLKREQ#
66 	 *  5-USB3 overcurrent
67 	 *  6-USB3 power
68 	 *  7-CON2 W_DISABLE
69 	 *  8-JP4 P1
70 	 *  9-JP4 P4
71 	 * 10-JP4 P5
72 	 * 11-m.2 DEVSLP
73 	 * 12-SFP_LOS
74 	 * 13-SFP_TX_FAULT
75 	 * 14-SFP_TX_DISABLE
76 	 * 15-SFP_MOD_DEF0
78 	pcie2-0-clkreq-hog {
79 		gpio-hog;
80 		gpios = <4 GPIO_ACTIVE_LOW>;
82 		line-name = "pcie2.0-clkreq";
84 	pcie2-0-w-disable-hog {
85 		gpio-hog;
86 		gpios = <7 GPIO_ACTIVE_LOW>;
87 		output-low;
88 		line-name = "pcie2.0-w-disable";
97 		#address-cells = <1>;
98 		#size-cells = <0>;
100 		pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
101 		pinctrl-names = "default";
104 			#address-cells = <1>;
105 			#size-cells = <0>;
135 				phy-mode = "1000base-x";
137 				fixed-link {
139 					full-duplex;
147 				phy-mode = "rgmii-id";
149 				fixed-link {
151 					full-duplex;
159 	clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
163 	clearfog_dsa0_pins: clearfog-dsa0-pins {
167 	clearfog_spi1_cs_pins: spi1-cs-pins {
171 	rear_button_pins: rear-button-pins {
184 	pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;