Lines Matching +full:armada +full:- +full:370 +full:- +full:gpio
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 375 family SoC
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/phy/phy.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
21 model = "Marvell Armada 375 family SoC";
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <1000000000>;
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
48 #address-cells = <1>;
49 #size-cells = <0>;
50 enable-method = "marvell,armada-375-smp";
54 compatible = "arm,cortex-a9";
59 compatible = "arm,cortex-a9";
65 compatible = "arm,cortex-a9-pmu";
66 interrupts-extended = <&mpic 3>;
70 compatible = "marvell,armada375-mbus", "simple-bus";
71 #address-cells = <2>;
72 #size-cells = <1>;
74 interrupt-parent = <&gic>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
83 devbus_bootcs: devbus-bootcs {
84 compatible = "marvell,mvebu-devbus";
87 #address-cells = <1>;
88 #size-cells = <1>;
93 devbus_cs0: devbus-cs0 {
94 compatible = "marvell,mvebu-devbus";
97 #address-cells = <1>;
98 #size-cells = <1>;
103 devbus_cs1: devbus-cs1 {
104 compatible = "marvell,mvebu-devbus";
107 #address-cells = <1>;
108 #size-cells = <1>;
113 devbus_cs2: devbus-cs2 {
114 compatible = "marvell,mvebu-devbus";
117 #address-cells = <1>;
118 #size-cells = <1>;
123 devbus_cs3: devbus-cs3 {
124 compatible = "marvell,mvebu-devbus";
127 #address-cells = <1>;
128 #size-cells = <1>;
133 internal-regs {
134 compatible = "simple-bus";
135 #address-cells = <1>;
136 #size-cells = <1>;
139 L2: cache-controller@8000 {
140 compatible = "arm,pl310-cache";
142 cache-unified;
143 cache-level = <2>;
144 arm,double-linefill-incr = <0>;
145 arm,double-linefill-wrap = <0>;
146 arm,double-linefill = <0>;
147 prefetch-data = <1>;
151 compatible = "arm,cortex-a9-scu";
156 compatible = "arm,cortex-a9-twd-timer";
162 gic: interrupt-controller@d000 {
163 compatible = "arm,cortex-a9-gic";
164 #interrupt-cells = <3>;
165 #size-cells = <0>;
166 interrupt-controller;
172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "marvell,orion-mdio";
181 #address-cells = <1>;
182 #size-cells = <0>;
183 compatible = "marvell,armada-375-pp2";
189 clock-names = "pp_clk", "gop_clk";
192 eth0: ethernet-port@0 {
195 port-id = <0>; /* For backward compatibility. */
199 eth1: ethernet-port@1 {
202 port-id = <1>; /* For backward compatibility. */
208 compatible = "marvell,orion-rtc";
214 compatible = "marvell,armada-375-spi",
215 "marvell,orion-spi";
217 #address-cells = <1>;
218 #size-cells = <0>;
219 cell-index = <0>;
226 compatible = "marvell,armada-375-spi",
227 "marvell,orion-spi";
229 #address-cells = <1>;
230 #size-cells = <0>;
231 cell-index = <1>;
238 compatible = "marvell,mv64xxx-i2c";
240 #address-cells = <1>;
241 #size-cells = <0>;
248 compatible = "marvell,mv64xxx-i2c";
250 #address-cells = <1>;
251 #size-cells = <0>;
258 compatible = "snps,dw-apb-uart";
260 reg-shift = <2>;
262 reg-io-width = <1>;
268 compatible = "snps,dw-apb-uart";
270 reg-shift = <2>;
272 reg-io-width = <1>;
278 compatible = "marvell,mv88f6720-pinctrl";
281 i2c0_pins: i2c0-pins {
286 i2c1_pins: i2c1-pins {
291 nand_pins: nand-pins {
300 sdio_pins: sdio-pins {
306 spi0_pins: spi0-pins {
313 gpio0: gpio@18100 {
314 compatible = "marvell,orion-gpio";
317 gpio-controller;
318 #gpio-cells = <2>;
319 interrupt-controller;
320 #interrupt-cells = <2>;
327 gpio1: gpio@18140 {
328 compatible = "marvell,orion-gpio";
331 gpio-controller;
332 #gpio-cells = <2>;
333 interrupt-controller;
334 #interrupt-cells = <2>;
341 gpio2: gpio@18180 {
342 compatible = "marvell,orion-gpio";
345 gpio-controller;
346 #gpio-cells = <2>;
347 interrupt-controller;
348 #interrupt-cells = <2>;
352 systemc: system-controller@18200 {
353 compatible = "marvell,armada-375-system-controller";
357 gateclk: clock-gating-control@18220 {
358 compatible = "marvell,armada-375-gating-clock";
361 #clock-cells = <1>;
364 usbcluster: usb-cluster@18400 {
365 compatible = "marvell,armada-375-usb-cluster";
367 #phy-cells = <1>;
370 mbusc: mbus-controller@20000 {
371 compatible = "marvell,mbus-controller";
375 mpic: interrupt-controller@20a00 {
378 #interrupt-cells = <1>;
379 #size-cells = <1>;
380 interrupt-controller;
381 msi-controller;
386 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
388 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
395 clock-names = "nbclk", "fixed";
399 compatible = "marvell,armada-375-wdt";
402 clock-names = "nbclk", "fixed";
406 compatible = "marvell,armada-370-cpu-reset";
410 coherencyfab: coherency-fabric@21010 {
411 compatible = "marvell,armada-375-coherency-fabric";
416 compatible = "marvell,orion-ehci";
421 phy-names = "usb";
426 compatible = "marvell,orion-ehci";
434 compatible = "marvell,armada-375-xhci";
439 phy-names = "usb";
444 compatible = "marvell,orion-xor";
464 compatible = "marvell,orion-xor";
484 compatible = "marvell,armada-375-crypto";
486 reg-names = "regs";
491 clock-names = "cesa0", "cesa1",
493 marvell,crypto-srams = <&crypto_sram0>,
495 marvell,crypto-sram-size = <0x800>;
499 compatible = "marvell,armada-370-sata";
503 clock-names = "0", "1";
507 nand_controller: nand-controller@d0000 {
508 compatible = "marvell,armada370-nand-controller";
510 #address-cells = <1>;
511 #size-cells = <0>;
518 compatible = "marvell,orion-sdio";
522 bus-width = <4>;
523 cap-sdio-irq;
524 cap-sd-highspeed;
525 cap-mmc-highspeed;
530 compatible = "marvell,armada375-thermal";
535 coreclk: mvebu-sar@e8204 {
536 compatible = "marvell,armada-375-core-clock";
538 #clock-cells = <1>;
541 coredivclk: corediv-clock@e8250 {
542 compatible = "marvell,armada-375-corediv-clock";
544 #clock-cells = <1>;
546 clock-output-names = "nand";
551 compatible = "marvell,armada-370-pcie";
555 #address-cells = <3>;
556 #size-cells = <2>;
558 msi-parent = <&mpic>;
559 bus-range = <0x00 0xff>;
571 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
573 #address-cells = <3>;
574 #size-cells = <2>;
575 interrupt-names = "intx";
576 interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
577 #interrupt-cells = <1>;
580 bus-range = <0x00 0xff>;
581 interrupt-map-mask = <0 0 0 7>;
582 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
586 marvell,pcie-port = <0>;
587 marvell,pcie-lane = <0>;
591 pcie0_intc: interrupt-controller {
592 interrupt-controller;
593 #interrupt-cells = <1>;
599 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
601 #address-cells = <3>;
602 #size-cells = <2>;
603 interrupt-names = "intx";
604 interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
605 #interrupt-cells = <1>;
608 bus-range = <0x00 0xff>;
609 interrupt-map-mask = <0 0 0 7>;
610 interrupt-map = <0 0 0 1 &pcie1_intc 0>,
614 marvell,pcie-port = <0>;
615 marvell,pcie-lane = <1>;
619 pcie1_intc: interrupt-controller {
620 interrupt-controller;
621 #interrupt-cells = <1>;
627 crypto_sram0: sa-sram0 {
628 compatible = "mmio-sram";
631 #address-cells = <1>;
632 #size-cells = <1>;
636 crypto_sram1: sa-sram1 {
637 compatible = "mmio-sram";
640 #address-cells = <1>;
641 #size-cells = <1>;