intel/ixp/intel-ixp43x-gateworks-gw2358.dts

13 	#address-cells = <1>;
14 	#size-cells = <1>;
46 		#address-cells = <1>;
85 				intel,ixp4xx-eb-write-enable = <1>;
105 				intel,ixp4xx-eb-t1 = <3>; // 3 cycles extra address phase
106 				intel,ixp4xx-eb-t2 = <3>; // 3 cycles extra setup phase
107 				intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
108 				intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
109 				intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
110 				intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
111 				intel,ixp4xx-eb-byte-access-on-halfword = <1>;
112 				intel,ixp4xx-eb-mux-address-and-data = <0>;
113 				intel,ixp4xx-eb-ahb-split-transfers = <0>;
114 				intel,ixp4xx-eb-write-enable = <1>;
115 				intel,ixp4xx-eb-byte-access = <1>;
129 			 * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2
132 			 * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
134 			#interrupt-cells = <1>;
137 			/* IDSEL 1 */
138 			<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
139 			<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
140 			<0x0800 0 0 3 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
141 			<0x0800 0 0 4 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
143 			<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
148 			<0x1800 0 0 1 &gpio0 9  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
153 			<0x2000 0 0 1 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
158 			<0x3000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 10 */
163 			<0x7800 0 0 1 &gpio0 8  IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 8 */
177 				#address-cells = <1>;
180 				phy1: ethernet-phy@1 {
181 					reg = <1>;