Lines Matching +full:1 +full:eb
16 #address-cells = <1>;
17 #size-cells = <1>;
55 intel,ixp4xx-eb-t3 = <3>;
56 intel,ixp4xx-eb-byte-access-on-halfword = <1>;
57 intel,ixp4xx-eb-write-enable = <1>;
71 intel,ixp4xx-eb-t3 = <1>;
72 intel,ixp4xx-eb-t4 = <2>;
73 intel,ixp4xx-eb-ahb-split-transfers = <1>;
74 intel,ixp4xx-eb-write-enable = <1>;
75 intel,ixp4xx-eb-byte-access = <1>;
90 intel,ixp4xx-eb-t3 = <3>;
91 intel,ixp4xx-eb-cycle-type = <1>; /* Motorola cycles */
92 intel,ixp4xx-eb-write-enable = <1>;
93 intel,ixp4xx-eb-byte-access = <1>;
102 intel,ixp4xx-eb-write-enable = <1>;
103 intel,ixp4xx-eb-byte-access = <1>;
109 intel,ixp4xx-eb-write-enable = <1>;
110 intel,ixp4xx-eb-byte-access = <1>;
120 * We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt
123 #interrupt-cells = <1>;
126 /* IDSEL 1 */
127 <0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */
128 <0x0800 0 0 2 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 2 */
129 <0x0800 0 0 3 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 2 */
130 <0x0800 0 0 4 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 2 */
132 <0x1000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 3 */
147 #address-cells = <1>;
154 phy1: ethernet-phy@1 {
155 reg = <1>;