Lines Matching +full:sda +full:- +full:pins
1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <27000000>;
24 clock-output-names = "27MHz-clock";
27 clk_108MHz: clk-108M {
28 #clock-cells = <0>;
29 compatible = "fixed-clock";
30 clock-frequency = <108000000>;
31 clock-output-names = "108MHz-clock";
38 * BCM2711-specific peripherals
39 * ARM-local peripherals
44 /* Emulate a contiguous 30-bit address range for DMA */
45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
48 * This node is the provider for the enable-method for
51 local_intc: interrupt-controller@40000000 {
52 compatible = "brcm,bcm2836-l1-intc";
56 gicv2: interrupt-controller@40041000 {
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 compatible = "arm,gic-400";
68 avs_monitor: avs-monitor@7d5d2000 {
69 compatible = "brcm,bcm2711-avs-monitor",
70 "syscon", "simple-mfd";
74 compatible = "brcm,bcm2711-thermal";
75 #thermal-sensor-cells = <0>;
79 dma: dma-controller@7e007000 {
80 compatible = "brcm,bcm2835-dma";
89 /* DMA lite 7 - 10 */
94 interrupt-names = "dma0",
105 #dma-cells = <1>;
106 brcm,dma-channel-mask = <0x07f5>;
110 compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt";
111 #power-domain-cells = <1>;
112 #reset-cells = <1>;
116 reg-names = "pm", "asb", "rpivid_asb";
121 clock-names = "v3d", "peri_image", "h264", "isp";
122 system-power-controller;
126 compatible = "brcm,bcm2711-rng200";
136 clock-names = "uartclk", "apb_pclk";
137 arm,primecell-periphid = <0x00241011>;
147 clock-names = "uartclk", "apb_pclk";
148 arm,primecell-periphid = <0x00241011>;
158 clock-names = "uartclk", "apb_pclk";
159 arm,primecell-periphid = <0x00241011>;
169 clock-names = "uartclk", "apb_pclk";
170 arm,primecell-periphid = <0x00241011>;
175 compatible = "brcm,bcm2835-spi";
179 #address-cells = <1>;
180 #size-cells = <0>;
185 compatible = "brcm,bcm2835-spi";
189 #address-cells = <1>;
190 #size-cells = <0>;
195 compatible = "brcm,bcm2835-spi";
199 #address-cells = <1>;
200 #size-cells = <0>;
205 compatible = "brcm,bcm2835-spi";
209 #address-cells = <1>;
210 #size-cells = <0>;
215 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
219 #address-cells = <1>;
220 #size-cells = <0>;
225 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
229 #address-cells = <1>;
230 #size-cells = <0>;
235 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
239 #address-cells = <1>;
240 #size-cells = <0>;
245 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
249 #address-cells = <1>;
250 #size-cells = <0>;
255 compatible = "brcm,bcm2711-pixelvalve0";
262 compatible = "brcm,bcm2711-pixelvalve1";
269 compatible = "brcm,bcm2711-pixelvalve2";
276 compatible = "brcm,bcm2835-pwm";
279 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
280 assigned-clock-rates = <10000000>;
281 #pwm-cells = <3>;
286 compatible = "brcm,bcm2711-pixelvalve4";
293 compatible = "brcm,bcm2711-hvs";
299 compatible = "brcm,bcm2711-pixelvalve3";
306 compatible = "brcm,bcm2711-vec";
314 compatible = "brcm,brcm2711-dvp";
317 #clock-cells = <1>;
318 #reset-cells = <1>;
321 aon_intr: interrupt-controller@7ef00100 {
322 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
325 interrupt-controller;
326 #interrupt-cells = <1>;
330 compatible = "brcm,bcm2711-hdmi0";
340 reg-names = "hdmi",
349 clock-names = "hdmi", "bvb", "audio", "cec";
351 interrupt-parent = <&aon_intr>;
354 interrupt-names = "cec-tx", "cec-rx", "cec-low",
355 "wakeup", "hpd-connected", "hpd-removed";
358 dma-names = "audio-rx";
363 compatible = "brcm,bcm2711-hdmi-i2c";
365 reg-names = "bsc", "auto-i2c";
366 clock-frequency = <97500>;
371 compatible = "brcm,bcm2711-hdmi1";
381 reg-names = "hdmi",
391 clock-names = "hdmi", "bvb", "audio", "cec";
393 interrupt-parent = <&aon_intr>;
396 interrupt-names = "cec-tx", "cec-rx", "cec-low",
397 "wakeup", "hpd-connected", "hpd-removed";
399 dma-names = "audio-rx";
404 compatible = "brcm,bcm2711-hdmi-i2c";
406 reg-names = "bsc", "auto-i2c";
407 clock-frequency = <97500>;
416 * so, it'll edit the dma-ranges property below accordingly.
419 compatible = "simple-bus";
420 #address-cells = <2>;
421 #size-cells = <1>;
424 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
427 compatible = "brcm,bcm2711-emmc2";
435 arm-pmu {
436 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
441 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
445 compatible = "arm,armv8-timer";
455 arm,cpu-registers-not-fw-configured;
459 #address-cells = <1>;
460 #size-cells = <0>;
461 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
463 /* Source for d/i-cache-line-size and d/i-cache-sets
465 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en
466 * Source for d/i-cache-size
472 compatible = "arm,cortex-a72";
474 enable-method = "spin-table";
475 cpu-release-addr = <0x0 0x000000d8>;
476 d-cache-size = <0x8000>;
477 d-cache-line-size = <64>;
478 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
479 i-cache-size = <0xc000>;
480 i-cache-line-size = <64>;
481 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
482 next-level-cache = <&l2>;
487 compatible = "arm,cortex-a72";
489 enable-method = "spin-table";
490 cpu-release-addr = <0x0 0x000000e0>;
491 d-cache-size = <0x8000>;
492 d-cache-line-size = <64>;
493 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
494 i-cache-size = <0xc000>;
495 i-cache-line-size = <64>;
496 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
497 next-level-cache = <&l2>;
502 compatible = "arm,cortex-a72";
504 enable-method = "spin-table";
505 cpu-release-addr = <0x0 0x000000e8>;
506 d-cache-size = <0x8000>;
507 d-cache-line-size = <64>;
508 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
509 i-cache-size = <0xc000>;
510 i-cache-line-size = <64>;
511 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
512 next-level-cache = <&l2>;
517 compatible = "arm,cortex-a72";
519 enable-method = "spin-table";
520 cpu-release-addr = <0x0 0x000000f0>;
521 d-cache-size = <0x8000>;
522 d-cache-line-size = <64>;
523 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
524 i-cache-size = <0xc000>;
525 i-cache-line-size = <64>;
526 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
527 next-level-cache = <&l2>;
530 /* Source for d/i-cache-line-size and d/i-cache-sets
532 * /Level-2-Memory-System/About-the-L2-memory-system?lang=en
533 * Source for d/i-cache-size
537 l2: l2-cache0 {
539 cache-unified;
540 cache-size = <0x100000>;
541 cache-line-size = <64>;
542 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
543 cache-level = <2>;
548 compatible = "simple-bus";
549 #address-cells = <2>;
550 #size-cells = <1>;
556 compatible = "brcm,bcm2711-pcie";
559 #address-cells = <3>;
560 #interrupt-cells = <1>;
561 #size-cells = <2>;
564 interrupt-names = "pcie", "msi";
565 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
566 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
574 msi-controller;
575 msi-parent = <&pcie0>;
584 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
586 brcm,enable-ssc;
590 compatible = "brcm,bcm2711-genet-v5";
592 #address-cells = <0x1>;
593 #size-cells = <0x1>;
599 compatible = "brcm,genet-mdio-v5";
601 reg-names = "mdio";
602 #address-cells = <0x1>;
603 #size-cells = <0x0>;
608 compatible = "brcm,2711-v3d";
611 reg-names = "hub", "core0";
613 power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
621 clock-frequency = <54000000>;
625 compatible = "brcm,bcm2711-cprman";
629 coefficients = <(-487) 410040>;
630 thermal-sensors = <&thermal>;
639 compatible = "brcm,bcm2711-dsi1";
643 compatible = "brcm,bcm2711-gpio";
649 gpio-ranges = <&gpio 0 0 58>;
651 gpclk0_gpio49: gpclk0-gpio49 {
652 pin-gpclk {
653 pins = "gpio49";
655 bias-disable;
658 gpclk1_gpio50: gpclk1-gpio50 {
659 pin-gpclk {
660 pins = "gpio50";
662 bias-disable;
665 gpclk2_gpio51: gpclk2-gpio51 {
666 pin-gpclk {
667 pins = "gpio51";
669 bias-disable;
673 i2c0_gpio46: i2c0-gpio46 {
674 pin-sda {
676 pins = "gpio46";
677 bias-pull-up;
679 pin-scl {
681 pins = "gpio47";
682 bias-disable;
685 i2c1_gpio46: i2c1-gpio46 {
686 pin-sda {
688 pins = "gpio46";
689 bias-pull-up;
691 pin-scl {
693 pins = "gpio47";
694 bias-disable;
697 i2c3_gpio2: i2c3-gpio2 {
698 pin-sda {
700 pins = "gpio2";
701 bias-pull-up;
703 pin-scl {
705 pins = "gpio3";
706 bias-disable;
709 i2c3_gpio4: i2c3-gpio4 {
710 pin-sda {
712 pins = "gpio4";
713 bias-pull-up;
715 pin-scl {
717 pins = "gpio5";
718 bias-disable;
721 i2c4_gpio6: i2c4-gpio6 {
722 pin-sda {
724 pins = "gpio6";
725 bias-pull-up;
727 pin-scl {
729 pins = "gpio7";
730 bias-disable;
733 i2c4_gpio8: i2c4-gpio8 {
734 pin-sda {
736 pins = "gpio8";
737 bias-pull-up;
739 pin-scl {
741 pins = "gpio9";
742 bias-disable;
745 i2c5_gpio10: i2c5-gpio10 {
746 pin-sda {
748 pins = "gpio10";
749 bias-pull-up;
751 pin-scl {
753 pins = "gpio11";
754 bias-disable;
757 i2c5_gpio12: i2c5-gpio12 {
758 pin-sda {
760 pins = "gpio12";
761 bias-pull-up;
763 pin-scl {
765 pins = "gpio13";
766 bias-disable;
769 i2c6_gpio0: i2c6-gpio0 {
770 pin-sda {
772 pins = "gpio0";
773 bias-pull-up;
775 pin-scl {
777 pins = "gpio1";
778 bias-disable;
781 i2c6_gpio22: i2c6-gpio22 {
782 pin-sda {
784 pins = "gpio22";
785 bias-pull-up;
787 pin-scl {
789 pins = "gpio23";
790 bias-disable;
793 i2c_slave_gpio8: i2c-slave-gpio8 {
794 pins-i2c-slave {
795 pins = "gpio8",
803 jtag_gpio48: jtag-gpio48 {
804 pins-jtag {
805 pins = "gpio48",
815 mii_gpio28: mii-gpio28 {
816 pins-mii {
817 pins = "gpio28",
824 mii_gpio36: mii-gpio36 {
825 pins-mii {
826 pins = "gpio36",
834 pcm_gpio50: pcm-gpio50 {
835 pins-pcm {
836 pins = "gpio50",
844 pwm0_0_gpio12: pwm0-0-gpio12 {
845 pin-pwm {
846 pins = "gpio12";
848 bias-disable;
851 pwm0_0_gpio18: pwm0-0-gpio18 {
852 pin-pwm {
853 pins = "gpio18";
855 bias-disable;
858 pwm1_0_gpio40: pwm1-0-gpio40 {
859 pin-pwm {
860 pins = "gpio40";
862 bias-disable;
865 pwm0_1_gpio13: pwm0-1-gpio13 {
866 pin-pwm {
867 pins = "gpio13";
869 bias-disable;
872 pwm0_1_gpio19: pwm0-1-gpio19 {
873 pin-pwm {
874 pins = "gpio19";
876 bias-disable;
879 pwm1_1_gpio41: pwm1-1-gpio41 {
880 pin-pwm {
881 pins = "gpio41";
883 bias-disable;
886 pwm0_1_gpio45: pwm0-1-gpio45 {
887 pin-pwm {
888 pins = "gpio45";
890 bias-disable;
893 pwm0_0_gpio52: pwm0-0-gpio52 {
894 pin-pwm {
895 pins = "gpio52";
897 bias-disable;
900 pwm0_1_gpio53: pwm0-1-gpio53 {
901 pin-pwm {
902 pins = "gpio53";
904 bias-disable;
908 rgmii_gpio35: rgmii-gpio35 {
909 pin-start-stop {
910 pins = "gpio35";
913 pin-rx-ok {
914 pins = "gpio36";
918 rgmii_irq_gpio34: rgmii-irq-gpio34 {
919 pin-irq {
920 pins = "gpio34";
924 rgmii_irq_gpio39: rgmii-irq-gpio39 {
925 pin-irq {
926 pins = "gpio39";
930 rgmii_mdio_gpio28: rgmii-mdio-gpio28 {
931 pins-mdio {
932 pins = "gpio28",
937 rgmii_mdio_gpio37: rgmii-mdio-gpio37 {
938 pins-mdio {
939 pins = "gpio37",
945 spi0_gpio46: spi0-gpio46 {
946 pins-spi {
947 pins = "gpio46",
954 spi2_gpio46: spi2-gpio46 {
955 pins-spi {
956 pins = "gpio46",
964 spi3_gpio0: spi3-gpio0 {
965 pins-spi {
966 pins = "gpio0",
973 spi4_gpio4: spi4-gpio4 {
974 pins-spi {
975 pins = "gpio4",
982 spi5_gpio12: spi5-gpio12 {
983 pins-spi {
984 pins = "gpio12",
991 spi6_gpio18: spi6-gpio18 {
992 pins-spi {
993 pins = "gpio18",
1001 uart2_gpio0: uart2-gpio0 {
1002 pin-tx {
1003 pins = "gpio0";
1005 bias-disable;
1007 pin-rx {
1008 pins = "gpio1";
1010 bias-pull-up;
1013 uart2_ctsrts_gpio2: uart2-ctsrts-gpio2 {
1014 pin-cts {
1015 pins = "gpio2";
1017 bias-pull-up;
1019 pin-rts {
1020 pins = "gpio3";
1022 bias-disable;
1025 uart3_gpio4: uart3-gpio4 {
1026 pin-tx {
1027 pins = "gpio4";
1029 bias-disable;
1031 pin-rx {
1032 pins = "gpio5";
1034 bias-pull-up;
1037 uart3_ctsrts_gpio6: uart3-ctsrts-gpio6 {
1038 pin-cts {
1039 pins = "gpio6";
1041 bias-pull-up;
1043 pin-rts {
1044 pins = "gpio7";
1046 bias-disable;
1049 uart4_gpio8: uart4-gpio8 {
1050 pin-tx {
1051 pins = "gpio8";
1053 bias-disable;
1055 pin-rx {
1056 pins = "gpio9";
1058 bias-pull-up;
1061 uart4_ctsrts_gpio10: uart4-ctsrts-gpio10 {
1062 pin-cts {
1063 pins = "gpio10";
1065 bias-pull-up;
1067 pin-rts {
1068 pins = "gpio11";
1070 bias-disable;
1073 uart5_gpio12: uart5-gpio12 {
1074 pin-tx {
1075 pins = "gpio12";
1077 bias-disable;
1079 pin-rx {
1080 pins = "gpio13";
1082 bias-pull-up;
1085 uart5_ctsrts_gpio14: uart5-ctsrts-gpio14 {
1086 pin-cts {
1087 pins = "gpio14";
1089 bias-pull-up;
1091 pin-rts {
1092 pins = "gpio15";
1094 bias-disable;
1100 #address-cells = <2>;
1109 alloc-ranges = <0x0 0x00000000 0x40000000>;
1113 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1118 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1170 compatible = "brcm,bcm2711-vec";