Lines Matching +full:ddc +full:- +full:rx
1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/soc/bcm2835-pm.h>
10 #address-cells = <2>;
11 #size-cells = <1>;
13 interrupt-parent = <&gicv2>;
16 compatible = "brcm,bcm2711-vc5";
20 clk_27MHz: clk-27M {
21 #clock-cells = <0>;
22 compatible = "fixed-clock";
23 clock-frequency = <27000000>;
24 clock-output-names = "27MHz-clock";
27 clk_108MHz: clk-108M {
28 #clock-cells = <0>;
29 compatible = "fixed-clock";
30 clock-frequency = <108000000>;
31 clock-output-names = "108MHz-clock";
38 * BCM2711-specific peripherals
39 * ARM-local peripherals
44 /* Emulate a contiguous 30-bit address range for DMA */
45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
48 * This node is the provider for the enable-method for
51 local_intc: interrupt-controller@40000000 {
52 compatible = "brcm,bcm2836-l1-intc";
56 gicv2: interrupt-controller@40041000 {
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 compatible = "arm,gic-400";
68 avs_monitor: avs-monitor@7d5d2000 {
69 compatible = "brcm,bcm2711-avs-monitor",
70 "syscon", "simple-mfd";
74 compatible = "brcm,bcm2711-thermal";
75 #thermal-sensor-cells = <0>;
79 dma: dma-controller@7e007000 {
80 compatible = "brcm,bcm2835-dma";
89 /* DMA lite 7 - 10 */
94 interrupt-names = "dma0",
105 #dma-cells = <1>;
106 brcm,dma-channel-mask = <0x07f5>;
110 compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt";
111 #power-domain-cells = <1>;
112 #reset-cells = <1>;
116 reg-names = "pm", "asb", "rpivid_asb";
121 clock-names = "v3d", "peri_image", "h264", "isp";
122 system-power-controller;
126 compatible = "brcm,bcm2711-rng200";
136 clock-names = "uartclk", "apb_pclk";
137 arm,primecell-periphid = <0x00341011>;
147 clock-names = "uartclk", "apb_pclk";
148 arm,primecell-periphid = <0x00341011>;
158 clock-names = "uartclk", "apb_pclk";
159 arm,primecell-periphid = <0x00341011>;
169 clock-names = "uartclk", "apb_pclk";
170 arm,primecell-periphid = <0x00341011>;
175 compatible = "brcm,bcm2835-spi";
179 #address-cells = <1>;
180 #size-cells = <0>;
185 compatible = "brcm,bcm2835-spi";
189 #address-cells = <1>;
190 #size-cells = <0>;
195 compatible = "brcm,bcm2835-spi";
199 #address-cells = <1>;
200 #size-cells = <0>;
205 compatible = "brcm,bcm2835-spi";
209 #address-cells = <1>;
210 #size-cells = <0>;
215 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
219 #address-cells = <1>;
220 #size-cells = <0>;
225 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
229 #address-cells = <1>;
230 #size-cells = <0>;
235 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
239 #address-cells = <1>;
240 #size-cells = <0>;
245 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
249 #address-cells = <1>;
250 #size-cells = <0>;
255 compatible = "brcm,bcm2711-pixelvalve0";
262 compatible = "brcm,bcm2711-pixelvalve1";
269 compatible = "brcm,bcm2711-pixelvalve2";
276 compatible = "brcm,bcm2835-pwm";
279 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
280 assigned-clock-rates = <10000000>;
281 #pwm-cells = <3>;
286 compatible = "brcm,bcm2711-pixelvalve4";
293 compatible = "brcm,bcm2711-hvs";
299 compatible = "brcm,bcm2711-pixelvalve3";
306 compatible = "brcm,bcm2711-vec";
314 compatible = "brcm,brcm2711-dvp";
317 #clock-cells = <1>;
318 #reset-cells = <1>;
321 aon_intr: interrupt-controller@7ef00100 {
322 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
325 interrupt-controller;
326 #interrupt-cells = <1>;
330 compatible = "brcm,bcm2711-hdmi0";
340 reg-names = "hdmi",
349 clock-names = "hdmi", "bvb", "audio", "cec";
351 interrupt-parent = <&aon_intr>;
354 interrupt-names = "cec-tx", "cec-rx", "cec-low",
355 "wakeup", "hpd-connected", "hpd-removed";
356 ddc = <&ddc0>;
358 dma-names = "audio-rx";
363 compatible = "brcm,bcm2711-hdmi-i2c";
365 reg-names = "bsc", "auto-i2c";
366 clock-frequency = <97500>;
371 compatible = "brcm,bcm2711-hdmi1";
381 reg-names = "hdmi",
390 ddc = <&ddc1>;
391 clock-names = "hdmi", "bvb", "audio", "cec";
393 interrupt-parent = <&aon_intr>;
396 interrupt-names = "cec-tx", "cec-rx", "cec-low",
397 "wakeup", "hpd-connected", "hpd-removed";
399 dma-names = "audio-rx";
404 compatible = "brcm,bcm2711-hdmi-i2c";
406 reg-names = "bsc", "auto-i2c";
407 clock-frequency = <97500>;
416 * so, it'll edit the dma-ranges property below accordingly.
419 compatible = "simple-bus";
420 #address-cells = <2>;
421 #size-cells = <1>;
424 dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
427 compatible = "brcm,bcm2711-emmc2";
435 arm-pmu {
436 compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
441 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
445 compatible = "arm,armv8-timer";
457 #address-cells = <1>;
458 #size-cells = <0>;
459 enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
461 /* Source for d/i-cache-line-size and d/i-cache-sets
463 * /Level-1-Memory-System/About-the-L1-memory-system?lang=en
464 * Source for d/i-cache-size
470 compatible = "arm,cortex-a72";
472 enable-method = "spin-table";
473 cpu-release-addr = <0x0 0x000000d8>;
474 d-cache-size = <0x8000>;
475 d-cache-line-size = <64>;
476 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
477 i-cache-size = <0xc000>;
478 i-cache-line-size = <64>;
479 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
480 next-level-cache = <&l2>;
485 compatible = "arm,cortex-a72";
487 enable-method = "spin-table";
488 cpu-release-addr = <0x0 0x000000e0>;
489 d-cache-size = <0x8000>;
490 d-cache-line-size = <64>;
491 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
492 i-cache-size = <0xc000>;
493 i-cache-line-size = <64>;
494 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
495 next-level-cache = <&l2>;
500 compatible = "arm,cortex-a72";
502 enable-method = "spin-table";
503 cpu-release-addr = <0x0 0x000000e8>;
504 d-cache-size = <0x8000>;
505 d-cache-line-size = <64>;
506 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
507 i-cache-size = <0xc000>;
508 i-cache-line-size = <64>;
509 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
510 next-level-cache = <&l2>;
515 compatible = "arm,cortex-a72";
517 enable-method = "spin-table";
518 cpu-release-addr = <0x0 0x000000f0>;
519 d-cache-size = <0x8000>;
520 d-cache-line-size = <64>;
521 d-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
522 i-cache-size = <0xc000>;
523 i-cache-line-size = <64>;
524 i-cache-sets = <256>; // 48KiB(size)/64(line-size)=768ways/3-way set
525 next-level-cache = <&l2>;
528 /* Source for d/i-cache-line-size and d/i-cache-sets
530 * /Level-2-Memory-System/About-the-L2-memory-system?lang=en
531 * Source for d/i-cache-size
535 l2: l2-cache0 {
537 cache-unified;
538 cache-size = <0x100000>;
539 cache-line-size = <64>;
540 cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
541 cache-level = <2>;
546 compatible = "simple-bus";
547 #address-cells = <2>;
548 #size-cells = <1>;
554 compatible = "brcm,bcm2711-pcie";
557 #address-cells = <3>;
558 #interrupt-cells = <1>;
559 #size-cells = <2>;
562 interrupt-names = "pcie", "msi";
563 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
564 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
572 msi-controller;
573 msi-parent = <&pcie0>;
582 dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
584 brcm,enable-ssc;
588 compatible = "brcm,bcm2711-genet-v5";
590 #address-cells = <0x1>;
591 #size-cells = <0x1>;
597 compatible = "brcm,genet-mdio-v5";
599 reg-names = "mdio";
600 #address-cells = <0x1>;
601 #size-cells = <0x0>;
606 compatible = "brcm,2711-v3d";
609 reg-names = "hub", "core0";
611 power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
619 clock-frequency = <54000000>;
623 compatible = "brcm,bcm2711-cprman";
627 coefficients = <(-487) 410040>;
628 thermal-sensors = <&thermal>;
637 compatible = "brcm,bcm2711-dsi1";
641 compatible = "brcm,bcm2711-gpio";
647 gpio-ranges = <&gpio 0 0 58>;
649 gpclk0_gpio49: gpclk0-gpio49 {
650 pin-gpclk {
653 bias-disable;
656 gpclk1_gpio50: gpclk1-gpio50 {
657 pin-gpclk {
660 bias-disable;
663 gpclk2_gpio51: gpclk2-gpio51 {
664 pin-gpclk {
667 bias-disable;
671 i2c0_gpio46: i2c0-gpio46 {
672 pin-sda {
675 bias-pull-up;
677 pin-scl {
680 bias-disable;
683 i2c1_gpio46: i2c1-gpio46 {
684 pin-sda {
687 bias-pull-up;
689 pin-scl {
692 bias-disable;
695 i2c3_gpio2: i2c3-gpio2 {
696 pin-sda {
699 bias-pull-up;
701 pin-scl {
704 bias-disable;
707 i2c3_gpio4: i2c3-gpio4 {
708 pin-sda {
711 bias-pull-up;
713 pin-scl {
716 bias-disable;
719 i2c4_gpio6: i2c4-gpio6 {
720 pin-sda {
723 bias-pull-up;
725 pin-scl {
728 bias-disable;
731 i2c4_gpio8: i2c4-gpio8 {
732 pin-sda {
735 bias-pull-up;
737 pin-scl {
740 bias-disable;
743 i2c5_gpio10: i2c5-gpio10 {
744 pin-sda {
747 bias-pull-up;
749 pin-scl {
752 bias-disable;
755 i2c5_gpio12: i2c5-gpio12 {
756 pin-sda {
759 bias-pull-up;
761 pin-scl {
764 bias-disable;
767 i2c6_gpio0: i2c6-gpio0 {
768 pin-sda {
771 bias-pull-up;
773 pin-scl {
776 bias-disable;
779 i2c6_gpio22: i2c6-gpio22 {
780 pin-sda {
783 bias-pull-up;
785 pin-scl {
788 bias-disable;
791 i2c_slave_gpio8: i2c-slave-gpio8 {
792 pins-i2c-slave {
801 jtag_gpio48: jtag-gpio48 {
802 pins-jtag {
813 mii_gpio28: mii-gpio28 {
814 pins-mii {
822 mii_gpio36: mii-gpio36 {
823 pins-mii {
832 pcm_gpio50: pcm-gpio50 {
833 pins-pcm {
842 pwm0_0_gpio12: pwm0-0-gpio12 {
843 pin-pwm {
846 bias-disable;
849 pwm0_0_gpio18: pwm0-0-gpio18 {
850 pin-pwm {
853 bias-disable;
856 pwm1_0_gpio40: pwm1-0-gpio40 {
857 pin-pwm {
860 bias-disable;
863 pwm0_1_gpio13: pwm0-1-gpio13 {
864 pin-pwm {
867 bias-disable;
870 pwm0_1_gpio19: pwm0-1-gpio19 {
871 pin-pwm {
874 bias-disable;
877 pwm1_1_gpio41: pwm1-1-gpio41 {
878 pin-pwm {
881 bias-disable;
884 pwm0_1_gpio45: pwm0-1-gpio45 {
885 pin-pwm {
888 bias-disable;
891 pwm0_0_gpio52: pwm0-0-gpio52 {
892 pin-pwm {
895 bias-disable;
898 pwm0_1_gpio53: pwm0-1-gpio53 {
899 pin-pwm {
902 bias-disable;
906 rgmii_gpio35: rgmii-gpio35 {
907 pin-start-stop {
911 pin-rx-ok {
916 rgmii_irq_gpio34: rgmii-irq-gpio34 {
917 pin-irq {
922 rgmii_irq_gpio39: rgmii-irq-gpio39 {
923 pin-irq {
928 rgmii_mdio_gpio28: rgmii-mdio-gpio28 {
929 pins-mdio {
935 rgmii_mdio_gpio37: rgmii-mdio-gpio37 {
936 pins-mdio {
943 spi0_gpio46: spi0-gpio46 {
944 pins-spi {
952 spi2_gpio46: spi2-gpio46 {
953 pins-spi {
962 spi3_gpio0: spi3-gpio0 {
963 pins-spi {
971 spi4_gpio4: spi4-gpio4 {
972 pins-spi {
980 spi5_gpio12: spi5-gpio12 {
981 pins-spi {
989 spi6_gpio18: spi6-gpio18 {
990 pins-spi {
999 uart2_gpio0: uart2-gpio0 {
1000 pin-tx {
1003 bias-disable;
1005 pin-rx {
1008 bias-pull-up;
1011 uart2_ctsrts_gpio2: uart2-ctsrts-gpio2 {
1012 pin-cts {
1015 bias-pull-up;
1017 pin-rts {
1020 bias-disable;
1023 uart3_gpio4: uart3-gpio4 {
1024 pin-tx {
1027 bias-disable;
1029 pin-rx {
1032 bias-pull-up;
1035 uart3_ctsrts_gpio6: uart3-ctsrts-gpio6 {
1036 pin-cts {
1039 bias-pull-up;
1041 pin-rts {
1044 bias-disable;
1047 uart4_gpio8: uart4-gpio8 {
1048 pin-tx {
1051 bias-disable;
1053 pin-rx {
1056 bias-pull-up;
1059 uart4_ctsrts_gpio10: uart4-ctsrts-gpio10 {
1060 pin-cts {
1063 bias-pull-up;
1065 pin-rts {
1068 bias-disable;
1071 uart5_gpio12: uart5-gpio12 {
1072 pin-tx {
1075 bias-disable;
1077 pin-rx {
1080 bias-pull-up;
1083 uart5_ctsrts_gpio14: uart5-ctsrts-gpio14 {
1084 pin-cts {
1087 bias-pull-up;
1089 pin-rts {
1092 bias-disable;
1098 #address-cells = <2>;
1107 alloc-ranges = <0x0 0x00000000 0x40000000>;
1111 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1116 compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
1156 arm,primecell-periphid = <0x00341011>;
1169 compatible = "brcm,bcm2711-vec";