Lines Matching +full:0 +full:x34000000
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
60 secondary-boot-reg = <0x35004178>;
69 secondary-boot-reg = <0x35004178>;
78 secondary-boot-reg = <0x35004178>;
87 ranges = <0 0x34000000 0x102f83ac>;
93 reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
98 reg = <0x01001f00 0x24>;
103 reg = <0x01003000 0x524>;
116 reg = <0x01006000 0x1c>;
125 ranges = <0 0x3e000000 0x0001c070>;
129 uartb: serial@0 {
131 reg = <0x00000000 0x118>;
141 reg = <0x00001000 0x118>;
151 reg = <0x00002000 0x118>;
161 reg = <0x00016000 0x70>;
164 #size-cells = <0>;
171 reg = <0x00017000 0x70>;
174 #size-cells = <0>;
181 reg = <0x00018000 0x70>;
184 #size-cells = <0>;
191 reg = <0x0001c000 0x70>;
194 #size-cells = <0>;
203 ranges = <0 0x3e300000 0x01b77000>;
209 reg = <0x00e20000 0x10000>;
220 reg = <0x00e30000 0x28>;
221 #phy-cells = <0>;
227 reg = <0x00e80000 0x801c>;
235 reg = <0x00e90000 0x801c>;
243 reg = <0x00ea0000 0x801c>;
251 reg = <0x00eb0000 0x801c>;
259 reg = <0x01b0e000 0x78>;
265 #address-cells = <0>;
267 reg = <0x01b21000 0x1000>,
268 <0x01b22000 0x1000>;
283 #clock-cells = <0>;
289 #clock-cells = <0>;
295 #clock-cells = <0>;
301 #clock-cells = <0>;
307 #clock-cells = <0>;
313 #clock-cells = <0>;
319 #clock-cells = <0>;
325 #clock-cells = <0>;
331 #clock-cells = <0>;
337 #clock-cells = <0>;
343 #clock-cells = <0>;
349 #clock-cells = <0>;
355 #clock-cells = <0>;
361 #clock-cells = <0>;
367 #clock-cells = <0>;
374 reg = <0x35001000 0x0f00>;
381 reg = <0x35002000 0x0f00>;
388 reg = <0x3e011000 0x0f00>;
401 reg = <0x3f001000 0x0f00>;