Lines Matching +full:syscon +full:- +full:clkset
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
6 #include <dt-bindings/clock/bcm-nsp.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
17 chipcommon-a-bus@18000000 {
18 compatible = "simple-bus";
20 #address-cells = <1>;
21 #size-cells = <1>;
36 pinctrl-names = "default";
37 pinctrl-0 = <&pinmux_uart1>;
42 mpcore-bus@19000000 {
43 compatible = "simple-bus";
45 #address-cells = <1>;
46 #size-cells = <1>;
49 compatible = "arm,cortex-a9-scu";
54 compatible = "arm,cortex-a9-global-timer";
61 compatible = "arm,cortex-a9-twd-timer";
68 gic: interrupt-controller@21000 {
69 compatible = "arm,cortex-a9-gic";
70 #interrupt-cells = <3>;
71 #address-cells = <0>;
72 interrupt-controller;
77 L2: cache-controller@22000 {
78 compatible = "arm,pl310-cache";
80 cache-unified;
81 arm,shared-override;
82 prefetch-data = <1>;
83 prefetch-instr = <1>;
84 cache-level = <2>;
89 compatible = "brcm,bus-axi";
92 #address-cells = <1>;
93 #size-cells = <1>;
95 #interrupt-cells = <1>;
96 interrupt-map-mask = <0x000fffff 0xffff>;
97 interrupt-map =
171 gpio-controller;
172 #gpio-cells = <2>;
173 interrupt-controller;
174 #interrupt-cells = <2>;
180 #address-cells = <3>;
181 #size-cells = <2>;
187 #address-cells = <3>;
188 #size-cells = <2>;
194 #address-cells = <3>;
195 #size-cells = <2>;
201 #address-cells = <1>;
202 #size-cells = <1>;
205 interrupt-parent = <&gic>;
208 compatible = "generic-ehci";
213 #address-cells = <1>;
214 #size-cells = <0>;
218 #trigger-source-cells = <0>;
223 #trigger-source-cells = <0>;
228 compatible = "generic-ohci";
232 #address-cells = <1>;
233 #size-cells = <0>;
237 #trigger-source-cells = <0>;
242 #trigger-source-cells = <0>;
250 #address-cells = <1>;
251 #size-cells = <1>;
254 interrupt-parent = <&gic>;
257 compatible = "generic-xhci";
261 phy-names = "usb";
263 #address-cells = <1>;
264 #size-cells = <0>;
268 #trigger-source-cells = <0>;
275 phy-mode = "internal";
277 fixed-link {
279 full-duplex;
285 phy-mode = "internal";
287 fixed-link {
289 full-duplex;
295 phy-mode = "internal";
297 fixed-link {
299 full-duplex;
309 compatible = "brcm,iproc-pwm";
312 #pwm-cells = <3>;
317 compatible = "brcm,iproc-mdio";
319 #size-cells = <0>;
320 #address-cells = <1>;
324 compatible = "brcm,bcm5301x-rng";
328 srab: ethernet-switch@18007000 {
329 compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab";
335 #address-cells = <1>;
336 #size-cells = <0>;
372 fixed-link {
374 full-duplex;
385 reg-shift = <2>;
389 dmu-bus@1800c000 {
390 compatible = "simple-bus";
392 #address-cells = <1>;
393 #size-cells = <1>;
395 cru-bus@100 {
396 compatible = "brcm,ns-cru", "simple-mfd";
399 #address-cells = <1>;
400 #size-cells = <1>;
403 compatible = "brcm,ns-usb2-phy";
405 brcm,syscon-clkset = <&cru_clkset>;
407 clock-names = "phy-ref-clk";
408 #phy-cells = <0>;
411 cru_clkset: syscon@180 {
412 compatible = "brcm,cru-clkset", "syscon";
417 compatible = "brcm,bcm4708-pinmux";
419 reg-names = "cru_gpio_control";
421 spi-pins {
426 pinmux_i2c: i2c-pins {
431 pinmux_pwm: pwm-pins {
437 pinmux_uart1: uart1-pins {
444 compatible = "brcm,ns-thermal";
446 #thermal-sensor-cells = <0>;
451 nand_controller: nand-controller@18028000 {
452 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
454 reg-names = "nand", "iproc-idm", "iproc-ext";
457 #address-cells = <1>;
458 #size-cells = <0>;
460 brcm,nand-has-wp;
463 thermal-zones {
464 cpu_thermal: cpu-thermal {
465 polling-delay-passive = <0>;
466 polling-delay = <1000>;
467 coefficients = <(-556) 418000>;
468 thermal-sensors = <&thermal>;
471 cpu-crit {
478 cooling-maps {