dts/broadcom/bcm-ns.dtsi

19 		ranges = <0x00000000 0x18000000 0x00001000>;
25 			reg = <0x0300 0x100>;
33 			reg = <0x0400 0x100>;
37 			pinctrl-0 = <&pinmux_uart1>;
44 		ranges = <0x00000000 0x19000000 0x00023000>;
50 			reg = <0x20000 0x100>;
55 			reg = <0x20200 0x100>;
62 			reg = <0x20600 0x20>;
71 			#address-cells = <0>;
73 			reg = <0x21000 0x1000>,
74 			      <0x20100 0x100>;
79 			reg = <0x22000 0x1000>;
90 		reg = <0x18000000 0x1000>;
91 		ranges = <0x00000000 0x18000000 0x00100000>;
96 		interrupt-map-mask = <0x000fffff 0xffff>;
99 			<0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
102 			<0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
103 			<0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
104 			<0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
105 			<0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
106 			<0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
107 			<0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
108 			<0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
109 			<0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
110 			<0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
111 			<0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
112 			<0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
113 			<0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
114 			<0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
116 			/* PCIe Controller 0 */
117 			<0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
118 			<0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
119 			<0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
120 			<0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
121 			<0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
122 			<0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
125 			<0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
126 			<0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
127 			<0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
128 			<0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
129 			<0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
130 			<0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
133 			<0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
134 			<0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
135 			<0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
136 			<0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
137 			<0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
138 			<0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
141 			<0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
144 			<0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
146 			/* Ethernet Controller 0 */
147 			<0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
150 			<0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
153 			<0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
156 			<0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
159 			<0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
160 			<0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
161 			<0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
162 			<0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
163 			<0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
164 			<0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
165 			<0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
166 			<0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
168 		chipcommon: chipcommon@0 {
169 			reg = <0x00000000 0x1000>;
178 			reg = <0x00012000 0x1000>;
185 			reg = <0x00013000 0x1000>;
192 			reg = <0x00014000 0x1000>;
199 			reg = <0x00021000 0x1000>;
209 				reg = <0x00021000 0x1000>;
214 				#size-cells = <0>;
218 					#trigger-source-cells = <0>;
223 					#trigger-source-cells = <0>;
229 				reg = <0x00022000 0x1000>;
233 				#size-cells = <0>;
237 					#trigger-source-cells = <0>;
242 					#trigger-source-cells = <0>;
248 			reg = <0x00023000 0x1000>;
258 				reg = <0x00023000 0x1000>;
264 				#size-cells = <0>;
268 					#trigger-source-cells = <0>;
274 			reg = <0x24000 0x800>;
284 			reg = <0x25000 0x800>;
294 			reg = <0x26000 0x800>;
304 			reg = <0x27000 0x800>;
310 		reg = <0x18002000 0x28>;
318 		reg = <0x18003000 0x8>;
319 		#size-cells = <0>;
325 		reg = <0x18004000 0x14>;
330 		reg = <0x18007000 0x1000>;
336 			#size-cells = <0>;
338 			port@0 {
339 				reg = <0>;
382 		reg = <0x18008000 0x20>;
391 		ranges = <0 0x1800c000 0x1000>;
397 			reg = <0x100 0x1a4>;
404 				reg = <0x164 0x4>;
408 				#phy-cells = <0>;
413 				reg = <0x180 0x4>;
418 				reg = <0x1c0 0x24>;
445 				reg = <0x2c0 0x10>;
446 				#thermal-sensor-cells = <0>;
453 		reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
458 		#size-cells = <0>;
465 			polling-delay-passive = <0>;
473 					hysteresis = <0>;