Lines Matching +full:0 +full:xca2
20 reg = <0x80000000 0x40000000>;
30 reg = <0x9f000000 0x01000000>; /* 16M */
34 size = <0x02000000>; /* 32M */
35 alignment = <0x01000000>;
46 gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
73 gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>;
79 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
88 flash@0 {
100 pinctrl-0 = <&pinctrl_spi1_default>;
101 flash@0 {
121 pinctrl-0 = <&pinctrl_rmii1_default>;
132 pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
139 pinctrl-0 = <&pinctrl_gpie0_default
198 reg = <0x50>;
208 reg = <0x48>;
214 reg = <0x49>;
220 reg = <0x70>;
229 reg = <0x70>;
234 reg = <0x71>;
239 reg = <0x72>;
253 reg = <0x70>;
262 reg = <0x70>;
271 reg = <0x33>;
276 reg = <0x32>;
281 reg = <0x20>;
290 reg = <0x23>;
292 #size-cells = <0>;
297 gpio@0 {
298 reg = <0>;
335 reg = <0x22>;
337 #size-cells = <0>;
342 gpio@0 {
343 reg = <0>;
385 reg = <0x20>;
387 #size-cells = <0>;
392 gpio@0 {
393 reg = <0>;
435 reg = <0x21>;
437 #size-cells = <0>;
442 gpio@0 {
443 reg = <0>;
494 reg = <0x24>;
496 #size-cells = <0>;
501 gpio@0 {
502 reg = <0>;
544 reg = <0x25>;
546 #size-cells = <0>;
551 gpio@0 {
552 reg = <0>;
593 reg = <0x58>;
598 reg = <0x59>;
613 pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default
618 fan@0 {
619 reg = <0x00>;
620 aspeed,fan-tach-ch = /bits/ 8 <0x00 0x01>;
624 reg = <0x01>;
625 aspeed,fan-tach-ch = /bits/ 8 <0x02 0x03>;
629 reg = <0x02>;
630 aspeed,fan-tach-ch = /bits/ 8 <0x04 0x05>;
634 reg = <0x03>;
635 aspeed,fan-tach-ch = /bits/ 8 <0x06 0x07>;
639 reg = <0x04>;
640 aspeed,fan-tach-ch = /bits/ 8 <0x08 0x09>;
644 reg = <0x05>;
645 aspeed,fan-tach-ch = /bits/ 8 <0x0a 0x0b>;
649 reg = <0x06>;
650 aspeed,fan-tach-ch = /bits/ 8 <0x0c 0x0d>;
654 reg = <0x07>;
655 aspeed,fan-tach-ch = /bits/ 8 <0x0e 0x0f>;
661 aspeed,lpc-io-reg = <0xca2>;
666 aspeed,lpc-io-reg = <0xca4>;
672 pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default