Lines Matching +full:0 +full:x01c19400
64 #clock-cells = <0>;
72 #clock-cells = <0>;
82 #size-cells = <0>;
84 cpu0: cpu@0 {
87 reg = <0>;
130 polling-delay-passive = <0>;
131 polling-delay = <0>;
132 thermal-sensors = <&ths 0>;
143 hysteresis = <0>;
161 polling-delay-passive = <0>;
162 polling-delay = <0>;
176 reg = <0x01000000 0x10000>;
187 compatible = "allwinner,sun8i-r40-de2-mixer-0";
188 reg = <0x01100000 0x100000>;
197 #size-cells = <0>;
210 reg = <0x01200000 0x100000>;
219 #size-cells = <0>;
233 reg = <0x01400000 0x20000>;
252 reg = <0x01c00000 0x30>;
259 reg = <0x01d00000 0xd0000>;
262 ranges = <0 0x01d00000 0xd0000>;
264 ve_sram: sram-section@0 {
267 reg = <0x000000 0x80000>;
276 reg = <0x01c00030 0x0c>;
277 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
283 reg = <0x01c02000 0x1000>;
295 reg = <0x01c05000 0x1000>;
302 #size-cells = <0>;
308 reg = <0x01c06000 0x1000>;
315 #size-cells = <0>;
321 reg = <0x01c09000 0x1000>;
334 reg = <0x01c0e000 0x1000>;
346 reg = <0x01c0f000 0x1000>;
351 pinctrl-0 = <&mmc0_pins>;
356 #size-cells = <0>;
362 reg = <0x01c10000 0x1000>;
370 #size-cells = <0>;
376 reg = <0x01c11000 0x1000>;
381 pinctrl-0 = <&mmc2_pins>;
386 #size-cells = <0>;
392 reg = <0x01c12000 0x1000>;
397 pinctrl-0 = <&mmc3_pins>;
402 #size-cells = <0>;
407 reg = <0x01c13400 0x14>,
408 <0x01c14800 0x4>,
409 <0x01c19800 0x4>,
410 <0x01c1c800 0x4>;
433 reg = <0x01c15000 0x1000>;
443 reg = <0x01c17000 0x1000>;
450 #size-cells = <0>;
455 reg = <0x01c18000 0x1000>;
465 reg = <0x01c19000 0x100>;
476 reg = <0x01c19400 0x100>;
488 reg = <0x01c1c000 0x100>;
499 reg = <0x01c1c400 0x100>;
512 reg = <0x01c1f000 0x1000>;
519 #size-cells = <0>;
524 reg = <0x01c20000 0x400>;
533 reg = <0x01c20400 0x400>;
542 reg = <0x01c20800 0x400>;
744 reg = <0x01c20c00 0x90>;
756 reg = <0x01c20c90 0x10>;
764 reg = <0x01c21800 0x400>;
765 pinctrl-0 = <&ir0_pins>;
777 reg = <0x01c21c00 0x400>;
778 pinctrl-0 = <&ir1_pins>;
788 #sound-dai-cells = <0>;
791 reg = <0x01c22000 0x400>;
801 #sound-dai-cells = <0>;
804 reg = <0x01c22400 0x400>;
814 #sound-dai-cells = <0>;
817 reg = <0x01c22800 0x400>;
828 reg = <0x01c24c00 0x100>;
839 reg = <0x01c28000 0x400>;
850 reg = <0x01c28400 0x400>;
861 reg = <0x01c28800 0x400>;
872 reg = <0x01c28c00 0x400>;
883 reg = <0x01c29000 0x400>;
894 reg = <0x01c29400 0x400>;
905 reg = <0x01c29800 0x400>;
916 reg = <0x01c29c00 0x400>;
927 reg = <0x01c2ac00 0x400>;
931 pinctrl-0 = <&i2c0_pins>;
935 #size-cells = <0>;
940 reg = <0x01c2b000 0x400>;
944 pinctrl-0 = <&i2c1_pins>;
948 #size-cells = <0>;
953 reg = <0x01c2b400 0x400>;
957 pinctrl-0 = <&i2c2_pins>;
961 #size-cells = <0>;
966 reg = <0x01c2b800 0x400>;
970 pinctrl-0 = <&i2c3_pins>;
974 #size-cells = <0>;
979 reg = <0x01c2bc00 0x400>;
988 reg = <0x01c2c000 0x400>;
992 pinctrl-0 = <&i2c4_pins>;
996 #size-cells = <0>;
1001 reg = <0x01c40000 0x10000>;
1024 reg = <0x01c50000 0x10000>;
1036 #size-cells = <0>;
1042 reg = <0x01c62000 0x1000>;
1046 dma-ranges = <0x00000000 0x40000000 0x80000000>;
1052 reg = <0x01c70000 0x1000>;
1073 #size-cells = <0>;
1075 tcon_top_mixer0_in: port@0 {
1076 reg = <0>;
1085 #size-cells = <0>;
1088 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
1089 reg = <0>;
1109 #size-cells = <0>;
1120 #size-cells = <0>;
1123 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
1124 reg = <0>;
1144 #size-cells = <0>;
1147 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
1148 reg = <0>;
1170 reg = <0x01c73000 0x1000>;
1180 #size-cells = <0>;
1182 tcon_tv0_in: port@0 {
1184 #size-cells = <0>;
1185 reg = <0>;
1187 tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
1188 reg = <0>;
1200 #size-cells = <0>;
1213 reg = <0x01c74000 0x1000>;
1223 #size-cells = <0>;
1225 tcon_tv1_in: port@0 {
1227 #size-cells = <0>;
1228 reg = <0>;
1230 tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
1231 reg = <0>;
1243 #size-cells = <0>;
1256 reg = <0x01c81000 0x1000>,
1257 <0x01c82000 0x2000>,
1258 <0x01c84000 0x2000>,
1259 <0x01c86000 0x2000>;
1268 reg = <0x01ee0000 0x10000>;
1282 #size-cells = <0>;
1284 hdmi_in: port@0 {
1285 reg = <0>;
1300 reg = <0x01ef0000 0x10000>;
1303 clock-names = "bus", "mod", "pll-0", "pll-1";
1306 #phy-cells = <0>;