Lines Matching refs:ccu
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
50 #include <dt-bindings/reset/sun6i-a31-ccu.h>
70 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
71 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
72 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
73 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
81 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
82 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
83 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
107 clocks = <&ccu CLK_CPU>;
122 clocks = <&ccu CLK_CPU>;
137 clocks = <&ccu CLK_CPU>;
152 clocks = <&ccu CLK_CPU>;
276 clocks = <&ccu CLK_AHB1_DMA>;
277 resets = <&ccu RST_AHB1_DMA>;
286 resets = <&ccu RST_AHB1_LCD0>,
287 <&ccu RST_AHB1_LVDS>;
290 clocks = <&ccu CLK_AHB1_LCD0>,
291 <&ccu CLK_LCD0_CH0>,
292 <&ccu CLK_LCD0_CH1>,
293 <&ccu 15>;
340 resets = <&ccu RST_AHB1_LCD1>,
341 <&ccu RST_AHB1_LVDS>;
343 clocks = <&ccu CLK_AHB1_LCD1>,
344 <&ccu CLK_LCD1_CH0>,
345 <&ccu CLK_LCD1_CH1>,
346 <&ccu 15>;
391 clocks = <&ccu CLK_AHB1_MMC0>,
392 <&ccu CLK_MMC0>,
393 <&ccu CLK_MMC0_OUTPUT>,
394 <&ccu CLK_MMC0_SAMPLE>;
399 resets = <&ccu RST_AHB1_MMC0>;
412 clocks = <&ccu CLK_AHB1_MMC1>,
413 <&ccu CLK_MMC1>,
414 <&ccu CLK_MMC1_OUTPUT>,
415 <&ccu CLK_MMC1_SAMPLE>;
420 resets = <&ccu RST_AHB1_MMC1>;
433 clocks = <&ccu CLK_AHB1_MMC2>,
434 <&ccu CLK_MMC2>,
435 <&ccu CLK_MMC2_OUTPUT>,
436 <&ccu CLK_MMC2_SAMPLE>;
441 resets = <&ccu RST_AHB1_MMC2>;
452 clocks = <&ccu CLK_AHB1_MMC3>,
453 <&ccu CLK_MMC3>,
454 <&ccu CLK_MMC3_OUTPUT>,
455 <&ccu CLK_MMC3_SAMPLE>;
460 resets = <&ccu RST_AHB1_MMC3>;
472 clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
473 <&ccu CLK_HDMI_DDC>,
474 <&ccu CLK_PLL_VIDEO0_2X>,
475 <&ccu CLK_PLL_VIDEO1_2X>;
477 resets = <&ccu RST_AHB1_HDMI>;
511 clocks = <&ccu CLK_AHB1_OTG>;
512 resets = <&ccu RST_AHB1_OTG>;
530 clocks = <&ccu CLK_USB_PHY0>,
531 <&ccu CLK_USB_PHY1>,
532 <&ccu CLK_USB_PHY2>;
536 resets = <&ccu RST_USB_PHY0>,
537 <&ccu RST_USB_PHY1>,
538 <&ccu RST_USB_PHY2>;
550 clocks = <&ccu CLK_AHB1_EHCI0>;
551 resets = <&ccu RST_AHB1_EHCI0>;
561 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
562 resets = <&ccu RST_AHB1_OHCI0>;
572 clocks = <&ccu CLK_AHB1_EHCI1>;
573 resets = <&ccu RST_AHB1_EHCI1>;
583 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
584 resets = <&ccu RST_AHB1_OHCI1>;
594 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
595 resets = <&ccu RST_AHB1_OHCI2>;
599 ccu: clock@1c20000 { label
600 compatible = "allwinner,sun6i-a31-ccu";
616 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>,
767 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
768 resets = <&ccu RST_APB1_SPDIF>;
780 clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
781 resets = <&ccu RST_APB1_DAUDIO0>;
793 clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
794 resets = <&ccu RST_APB1_DAUDIO1>;
822 clocks = <&ccu CLK_APB2_UART0>;
823 resets = <&ccu RST_APB2_UART0>;
835 clocks = <&ccu CLK_APB2_UART1>;
836 resets = <&ccu RST_APB2_UART1>;
848 clocks = <&ccu CLK_APB2_UART2>;
849 resets = <&ccu RST_APB2_UART2>;
861 clocks = <&ccu CLK_APB2_UART3>;
862 resets = <&ccu RST_APB2_UART3>;
874 clocks = <&ccu CLK_APB2_UART4>;
875 resets = <&ccu RST_APB2_UART4>;
887 clocks = <&ccu CLK_APB2_UART5>;
888 resets = <&ccu RST_APB2_UART5>;
898 clocks = <&ccu CLK_APB2_I2C0>;
899 resets = <&ccu RST_APB2_I2C0>;
911 clocks = <&ccu CLK_APB2_I2C1>;
912 resets = <&ccu RST_APB2_I2C1>;
924 clocks = <&ccu CLK_APB2_I2C2>;
925 resets = <&ccu RST_APB2_I2C2>;
937 clocks = <&ccu CLK_APB2_I2C3>;
938 resets = <&ccu RST_APB2_I2C3>;
949 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
951 resets = <&ccu RST_AHB1_EMAC>;
970 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
972 resets = <&ccu RST_AHB1_SS>;
981 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
983 resets = <&ccu RST_APB1_CODEC>;
997 clocks = <&ccu CLK_AHB1_HSTIMER>;
998 resets = <&ccu RST_AHB1_HSTIMER>;
1005 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
1009 resets = <&ccu RST_AHB1_SPI0>;
1019 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
1023 resets = <&ccu RST_AHB1_SPI1>;
1033 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
1037 resets = <&ccu RST_AHB1_SPI2>;
1047 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
1051 resets = <&ccu RST_AHB1_SPI3>;
1072 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1073 <&ccu CLK_DRAM_FE0>;
1076 resets = <&ccu RST_AHB1_FE0>;
1104 clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1105 <&ccu CLK_DRAM_FE1>;
1108 resets = <&ccu RST_AHB1_FE1>;
1136 clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1137 <&ccu CLK_DRAM_BE1>;
1140 resets = <&ccu RST_AHB1_BE1>;
1179 clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1180 <&ccu CLK_DRAM_DRC1>;
1183 resets = <&ccu RST_AHB1_DRC1>;
1222 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1223 <&ccu CLK_DRAM_BE0>;
1226 resets = <&ccu RST_AHB1_BE0>;
1262 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1263 <&ccu CLK_DRAM_DRC0>;
1266 resets = <&ccu RST_AHB1_DRC0>;
1325 <&ccu CLK_PLL_PERIPH>,
1326 <&ccu CLK_PLL_PERIPH>;