boot/compressed/head.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
5  *  Copyright (C) 1996-2002 Russell King
12 #include "efi-header.S"
20  AR_CLASS(	.arch	armv7-a	)
21  M_CLASS(	.arch	armv7-m	)
101 		kputc	#'-'
105 		kputc	#'-'
110 		kputc	#'-'
145 		mcr	p15, 0, \reg, c1, c0, 0	@ write SCTLR
154 		 * in little-endian form.
209  AR_CLASS(	sub	pc, pc, #3	)	@ A/R: switch to Thumb2 mode
234 		 * Booting from Angel - need to enter SVC mode and disable
251 		 * be needed here - is there an Angel SWI call for this?
269 		 * different platforms - we have chosen 128MB to allow
279 		mov	r0, pc
300 		 * No GOT fixup has occurred yet, but none of the code we're
319 		 * That means r4 < pc || r4 - 16k page directory > &_end.
323 		mov	r0, pc
326 		addcc	r0, r0, pc
377 		 * and folded into the former here. No GOT fixup has occurred
388 		/* preserve 64-bit alignment */
405 		 * If returned value is 1, there is no ATAG at the location
438 		/* preserve 64-bit alignment */
455  *   r4 - 16k page directory >= r10 -> OK
456  *   r4 + image length <= address of wont_overwrite -> OK
475 		 * Bump to the next 256-byte boundary with the size of
479 		add	r10, r10, #((reloc_code_end - restart + 256) & ~255)
525 1:		ldmdb	r6!, {r0 - r3, r10 - r12, lr}
527 		stmdb	r9!, {r0 - r3, r10 - r12, lr}
539 		mov	pc, r0
665 		.size	LC0, . - LC0
668 LC1:		.word	.L_user_stack_end - LC1	@ sp
669 		.word	_edata - LC1		@ r6
670 		.size	LC1, . - LC1
673 		.word	_end - restart + 16384 + 1024*1024
676 		.long	(input_data_end - 4) - .
681 		mov	pc, lr
687  * dcache_line_size - get the minimum D-cache line size from the CTR register
735 		mcr	p15, 0, r0, c2, c0, 0	@ D-cache on
736 		mcr	p15, 0, r0, c2, c0, 1	@ I-cache on
737 		mcr	p15, 0, r0, c3, c0, 0	@ write-buffer on
740 		mcr	p15, 0, r0, c5, c0, 1	@ I-access permission
741 		mcr	p15, 0, r0, c5, c0, 0	@ D-access permission
744 		mcr	p15, 0, r0, c7, c10, 4	@ drain write buffer
745 		mcr	p15, 0, r0, c7, c5, 0	@ flush(inval) I-Cache
746 		mcr	p15, 0, r0, c7, c6, 0	@ flush(inval) D-Cache
752 		mcr	p15, 0, r0, c1, c0, 0	@ write control reg
755 		mcr	p15, 0, r0, c7, c5, 0	@ flush(inval) I-Cache
756 		mcr	p15, 0, r0, c7, c6, 0	@ flush(inval) D-Cache
757 		mov	pc, lr
765 		mcr	p15, 0, r0, c3, c0, 0	@ write-buffer on
781 		mcr	p15, 0, r0, c1, c0, 0	@ write control reg
785 		mov	pc, lr
810 		orrlo	r1, r1, #0x10		@ Set XN|U for non-RAM
819  * so there is no map overlap problem for up to 1 MB compressed kernel.
824 		mov	r2, pc
831 		mov	pc, lr
838 		bic	r0, r0, #2		@ A (no unaligned access fault)
840 		mcr	p15, 0, r0, c1, c0, 0	@ write SCTLR
855 		mcr	p15, 0, r0, c7, c10, 4	@ drain write buffer
858 		orr	r0, r0, #0x5000		@ I-cache enable, RR cache replacement
860  ARM_BE8(	orr	r0, r0, #1 << 25 )	@ big-endian page tables
865 		mov	pc, r12
876 		mcr	p15, 0, r0, c7, c10, 4	@ drain write buffer
882 		orr	r0, r0, #0x5000		@ I-cache enable, RR cache replacement
883 		orr	r0, r0, #0x003c		@ write buffer
884 		bic	r0, r0, #2		@ A (no unaligned access fault)
888  ARM_BE8(	orr	r0, r0, #1 << 25 )	@ big-endian page tables
892 		bic     r6, r6, #1 << 31        @ 32-bit translation system
903 		mov	pc, r12
911 		mcr	p15, 0, r0, c7, c10, 4	@ drain write buffer
914 		orr	r0, r0, #0x1000		@ I-cache enable
918 		mov	pc, r12
923 		orr	r0, r0, #0x000d		@ Write buffer, mmu
925 		mov	r1, #-1
932 		sub	pc, lr, r0, lsr #32	@ properly flush pipeline
956 		 * On v7-M the processor id is located in the V7M_SCB_CPUID
958 		 * v7-M (if existant at all) we just return early here.
961 		 * use cp15 registers that are not implemented on v7-M.
971  ARM(		addeq	pc, r12, r3		) @ call cache function
973  THUMB(		moveq	pc, r12			) @ call cache function
979  *   - CPU ID match
980  *   - CPU ID mask
981  *   - 'cache on' method instruction
982  *   - 'cache off' method instruction
983  *   - 'cache flush' method instruction
996 		mov	pc, lr
998 		mov	pc, lr
1000 		mov	pc, lr
1005 		mov	pc, lr
1007 		mov	pc, lr
1009 		mov	pc, lr
1016 		mov	pc, lr
1031 		.word	0x41069260		@ ARM926EJ-S (v5TEJ)
1039 		mov	pc, lr
1041 		mov	pc, lr
1043 		mov	pc, lr
1127 		mov	pc, lr
1129 		mov	pc, lr
1131 		mov	pc, lr
1134 		.size	proc_types, . - proc_types
1137 		 * If you get a "non-constant expression in ".if" statement"
1142 		.if (. - proc_types) % PROC_ENTRY_SIZE != 0
1164 		mcr	p15, 0, r0, c7, c10, 4	@ drain write buffer
1165 		mcr	p15, 0, r0, c7, c6, 0	@ flush D-Cache
1166 		mcr	p15, 0, r0, c7, c5, 0	@ flush I-Cache
1167 		mov	pc, lr
1175 		mov	pc, lr
1186 		mov	pc, lr
1203 		mov	pc, lr
1224 		movne	pc, lr
1239 		mov	pc, lr
1243 		movne	pc, lr
1248 		mov	pc, lr
1257 		mov	pc, lr
1285 		mov	pc, lr
1289 		movne	pc, lr
1294 		mov	pc, lr
1298 		movne	pc, lr
1315 		mov	r1, pc
1328 		mov	pc, lr
1333 		movne	pc, lr
1336 		mov	pc, lr
1346 		.size	phexbuf, . - phexbuf
1367 		moveq	pc, lr
1377 		mov	pc, lr
1412 		mov	pc, r10
1438  ARM(		mov	pc, r4		)	@ call kernel
1448 		mcr	p15, 4, r0, c1, c0, 0	@ write HSCTLR
1464 		@ 32-bit addressable DRAM mapped 1:1 using short descriptors.
1467 		@ U-Boot might decide to enter the EFI stub in HYP mode
1525 0:		.long	.L_user_stack_end - .