Lines Matching refs:CREG_AXI_M_SLV1

179 #define CREG_AXI_M_SLV1(m)  ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x04))  macro
211 	writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_0));  in hsdk_init_memory_bridge_axi_dmac()
217 	writel(axi_m_slv1, CREG_AXI_M_SLV1(M_DMAC_1));  in hsdk_init_memory_bridge_axi_dmac()
234 	writel(0x63111111, CREG_AXI_M_SLV1(M_HS_CORE));  in hsdk_init_memory_bridge()
240 	writel(0x77777777, CREG_AXI_M_SLV1(M_HS_RTT));  in hsdk_init_memory_bridge()
246 	writel(0x88888888, CREG_AXI_M_SLV1(M_AXI_TUN));  in hsdk_init_memory_bridge()
252 	writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_VIDEO));  in hsdk_init_memory_bridge()
258 	writel(0x77777777, CREG_AXI_M_SLV1(M_HDMI_AUDIO));  in hsdk_init_memory_bridge()
264 	writel(0x77999999, CREG_AXI_M_SLV1(M_USB_HOST));  in hsdk_init_memory_bridge()
270 	writel(0x77999999, CREG_AXI_M_SLV1(M_ETHERNET));  in hsdk_init_memory_bridge()
276 	writel(0x77999999, CREG_AXI_M_SLV1(M_SDIO));  in hsdk_init_memory_bridge()
282 	writel(0x77777777, CREG_AXI_M_SLV1(M_GPU));  in hsdk_init_memory_bridge()
288 	writel(0x60000000, CREG_AXI_M_SLV1(M_DVFS));  in hsdk_init_memory_bridge()