Lines Matching refs:CREG_AXI_M_OFT0

180 #define CREG_AXI_M_OFT0(m)  ((void __iomem *)(CREG_BASE + 0x20 * (m) + 0x08))  macro
210 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_0));  in hsdk_init_memory_bridge_axi_dmac()
216 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_DMAC_1));  in hsdk_init_memory_bridge_axi_dmac()
235 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_CORE));  in hsdk_init_memory_bridge()
241 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HS_RTT));  in hsdk_init_memory_bridge()
247 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_AXI_TUN));  in hsdk_init_memory_bridge()
253 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_VIDEO));  in hsdk_init_memory_bridge()
259 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_HDMI_AUDIO));  in hsdk_init_memory_bridge()
265 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_USB_HOST));  in hsdk_init_memory_bridge()
271 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_ETHERNET));  in hsdk_init_memory_bridge()
277 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_SDIO));  in hsdk_init_memory_bridge()
283 	writel(0xFEDCBA98, CREG_AXI_M_OFT0(M_GPU));  in hsdk_init_memory_bridge()
289 	writel(0x00000000, CREG_AXI_M_OFT0(M_DVFS));  in hsdk_init_memory_bridge()