arc/kernel/entry-compact.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Low Level Interrupts/Traps/Exceptions(non-TLB) Handling for ARCompact ISA
5  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
6  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
9  *  -Userspace unaligned access emulation
12  *  -traced syscall return code (r0) was not saved into pt_regs for restoring
13  *   into user reg-file when traded task rets to user space.
14  *  -syscalls needing arch-wrappers (mainly for passing sp as pt_regs)
15  *   were not invoking post-syscall trace hook (jumping directly into
19  *  -Vector table jumps (@8 bytes) converted into branches (@4 bytes)
20  *  -To maintain the slot size of 8 bytes/vector, added nop, which is
24  *  -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
25  *  -Wrappers for sys_{,rt_}sigsuspend() no longer needed as they don't
29  *  -In a rare scenario, Process gets a Priv-V exception and gets scheduled
30  *   out. Since we don't do FAKE RTIE for Priv-V, CPU exception state remains
32  *   exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
38  *  -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
46  *  - r25 now contains the Current Task when in kernel
50  *    - MMU_SCRATCH0 Reg used for freeing up r9 in Level 1 ISR
51  *    - _current_task is made an array of NR_CPUS
52  *    - Access of _current_task wrapped inside a macro so that if hardware
134 ; ---------------------------------------------
144 ; ---------------------------------------------
146 ; ---------------------------------------------
151 	;------------------------------------------------------
154 	; This is to avoid a potential L1-L2-L1 scenario
155 	;  -L1 IRQ taken
156 	;  -L2 interrupts L1 (before L1 ISR could run)
157 	;  -preemption off IRQ, user task in syscall picked to run
158 	;  -RTIE to userspace
160 	;	But both L1 and L2 re-enabled, so another L1 can be taken
163 	;------------------------------------------------------
172 	; bump thread_info->preempt_count (Disable preemption)
179 	;------------------------------------------------------
181 	;------------------------------------------------------
189 	sr r8, [AUX_IRQ_LV12]       ; clear bit in Sticky Status Reg
197 ; ---------------------------------------------
200 ; ---------------------------------------------
222 ; ---------------------------------------------
224 ; ---------------------------------------------
244 	sr r8, [AUX_IRQ_LV12]       ; clear bit in Sticky Status Reg
249 ;################### Non TLB Exception Handling #############################
251 ; ---------------------------------------------
253 ; ---------------------------------------------
259 	;------ (5) Type of Protection Violation? ----------
262 	;   -Access Violation	: 00_23_(00|01|02|03)_00
264 	;   -Unaligned Access	: 00_23_04_00
271 	;========== (6b) Non aligned access ============
279 	; TBD: optimize - do this only if a callee reg was involved
280 	; either a dst of emulated LD/ST or src with address-writeback
306 ; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
321 	; Note that we use realtime STATUS32 (not pt_regs->status32) to
331 	; Level 2 interrupt return Path - from hardware standpoint
334 	;------------------------------------------------------------------
336 	; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret
342 	;------------------------------------------------------------------
347 	;----------------------------------------------------------------
352 	; decrement thread_info->preempt_count (re-enable preemption)