alpha/lib/ev6-csum_ipv6_magic.S

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * arch/alpha/lib/ev6-csum_ipv6_magic.S
4  * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
15  *	ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
17  *	E	- either cluster
18  *	U	- upper subcluster; U0 - subcluster U0; U1 - subcluster U1
19  *	L	- lower subcluster; L0 - subcluster L0; L1 - subcluster L1
32  * Then turn it back into a sign extended 32-bit item
35  * Swap <len> (an unsigned int) using Mike Burrows' 7-instruction sequence
36  * (we can't hide the 3-cycle latency of the unpkbw in the 6-instruction sequence)
41  * add carry bits + ushort --> ushort
42  * add carry bits + ushort --> ushort (in case the carry results in an overflow)
53  * may cause additional delay in rare cases (load-load replay traps).
65 	inslh	$18,7,$4	# U : 0000000000AABBCC
67 	sll	$19,8,$7	# U : U L U L : 0x00000000 00aabb00
69 	and	$16,7,$6	# E : src misalignment
74 	extql	$0,$6,$0	# U :
75 	extqh	$1,$6,$22	# U :
79 	cmoveq	$6,$31,$22	# E : src aligned?
82 	addl	$19,$7,$19	# E : U L U L : <sign bits>bbaabb00
84 	or	$0,$22,$0	# E : 1st src word complete
85 	extql	$1,$6,$1	# U :
86 	or	$18,$4,$18	# E : 000000CCDDAABBCC
87 	extqh	$5,$6,$5	# U : L U L U
89 	and	$17,7,$6	# E : dst misalignment
90 	extql	$2,$6,$2	# U :
91 	or	$1,$5,$1	# E : 2nd src word complete
92 	extqh	$3,$6,$22	# U : L U L U :
94 	cmoveq	$6,$31,$22	# E : dst aligned?
95 	extql	$3,$6,$3	# U :
96 	addq	$20,$0,$20	# E : begin summing the words
97 	extqh	$23,$6,$23	# U : L U L U :
100 	or	$2,$22,$2	# E : 1st dst word complete
102 	or	$3,$23,$3	# E : U L U L : 2nd dst word complete
104 	cmpult	$20,$0,$0	# E :
105 	addq	$20,$1,$20	# E :
109 	or	$18,$4,$18	# E : 00000000DDCCBBAA
110 	nop			# E :
111 	cmpult	$20,$1,$1	# E :
112 	addq	$20,$2,$20	# E : U L U L
114 	cmpult	$20,$2,$2	# E :
115 	addq	$20,$3,$20	# E :
116 	cmpult	$20,$3,$3	# E : (1 cycle stall on $20)
117 	addq	$20,$18,$20	# E : U L U L (1 cycle stall on $20)
119 	cmpult	$20,$18,$18	# E :
120 	addq	$20,$19,$20	# E : (1 cycle stall on $20)
121 	addq	$0,$1,$0	# E : merge the carries back into the csum
122 	addq	$2,$3,$2	# E :
124 	cmpult	$20,$19,$19	# E :
125 	addq	$18,$19,$18	# E : (1 cycle stall on $19)
126 	addq	$0,$2,$0	# E :
127 	addq	$20,$18,$20	# E : U L U L :
130 	addq	$0,$20,$0	# E :
132 	nop			# E :
135 	addq	$1,$0,$1	# E : Finished generating ulong
140 	addq	$0,$2,$0	# E
141 	addq	$0,$1,$3	# E : Finished generating uint
144 	nop			# E : L U L U
146 	addq	$1,$3,$0	# E : Final carry
147 	not	$0,$4		# E : complement (1 cycle stall on $0)