alpha/kernel/time.c

1 // SPDX-License-Identifier: GPL-2.0
8  * 1997-09-10	Updated NTP code according to technical memorandum Jan '96
10  * 1997-01-09    Adrian Sun
12  * 1997-10-29    John Bowman (bowman@math.ualberta.ca)
16  * 1999-04-16	Thorsten Kranzkowski (dl8bcu@gmx.net)
19  * 2003-06-03	R. Scott Bailey <scott.bailey@eds.com>
98 		ce->event_handler(ce);  in rtc_timer_interrupt()
112 	return -EINVAL;  in rtc_ce_set_next_event()
178 	ce->event_handler(ce);  in qemu_timer_interrupt()
253  * While we have free-running timecounters running on all CPUs, and we make
254  * a half-hearted attempt in init_rtc_rpcc_info to sync the timecounter
255  * with the wall clock, that initialization isn't kept up-to-date across
281    timing hardware for any one method to work everywhere.  :-(
296 		[EV56_CPU]   = {  333000000,  667000000 },  in validate_cc_value()
303 		/* None of the following are shipping as of 2001-11-01.  */  in validate_cc_value()
316 	cpu = (struct percpu_struct *)((char*)hwrpb + hwrpb->processor_offset);  in validate_cc_value()
317 	index = cpu->type & 0xffffffff;  in validate_cc_value()
327 	if (cc < cpu_hz[index].min - deviation  in validate_cc_value()
366 	cc = rpcc() - cc;  in calibrate_cc_with_pit()
376    When the Update-In-Progress (UIP) flag goes from 1 to 0, the
403 	/* Calibrate CPU clock -- attempt #1.  */  in time_init()
409 	/* Calibrate CPU clock -- attempt #2.  */  in time_init()
413 		est_cycle_freq = validate_cc_value(cc2 - cc1);  in time_init()
417 	cycle_freq = hwrpb->cycle_freq;  in time_init()
422 		diff = cycle_freq - est_cycle_freq;  in time_init()
424 			diff = -diff;  in time_init()
439 	if (hwrpb->nr_processors == 1)  in time_init()