Lines Matching +full:- +full:- +full:disable +full:- +full:replication
58 * er 28-Jan-1997 Initial Entry
67 ** The mask acts as a flag used in mapping actual ISA IRQs (0 - 15)
68 ** to device IRQs (A - H).
82 ** channels to device DMA channels (A - C).
216 ** CR00 - default value 0x28
219 ** 0x - 30ua pull-ups on nIDEEN, nHDCS0, NHDCS1
220 ** 11 - IRQ_H available as IRQ output,
222 ** 10 - nIDEEN, nHDCS0, nHDCS1 used to control IDE
245 ** CR01 - default value 0x9C
255 unsigned lock_crx: 1; /* Lock CR00 - CR18 */
260 ** CR02 - default value 0x88
273 ** CR03 - default value 0x78
276 ** ------- ------- ------
282 ** ------- ------- -------
295 unsigned drvden : 1; /* 1 = high, 0 - output */
302 ** CR04 - default value 0x00
306 ** 00 - Standard and Bidirectional
307 ** 01 - EPP mode and SPP
308 ** 10 - ECP mode
313 ** 11 - ECP mode and EPP mode
322 ** 00 - Normal
323 ** 01 - PPFD1
324 ** 10 - PPFD2
325 ** 11 - Reserved
337 ** 0 - Use pins IRRX, IRTX
338 ** 1 - Use pins IRRX2, IRTX2
357 ** CR05 - default value 0x00
360 ** 00 - Densel output normal
361 ** 01 - Reserved
362 ** 10 - Densel output 1
363 ** 11 - Densel output 0
370 unsigned fdc_dma_mode : 1; /* 0 = burst, 1 = non-burst */
379 ** CR06 - default value 0xFF
392 ** CR07 - default value 0x00
395 ** 0 - Auto Powerdown disabled (default)
396 ** 1 - Auto Powerdown enabled
415 ** CR08 - default value 0x00
426 ** CR09 - default value 0x00
429 ** 00 - ADRx disabled
430 ** 01 - 1 byte decode A<3:0> = 0000b
431 ** 10 - 8 byte block decode A<3:0> = 0XXXb
432 ** 11 - 16 byte block decode A<3:0> = XXXXb
445 ** CR0A - default value 0x00
456 ** CR0B - default value 0x00
469 ** CR0C - default value 0x00
472 ** 000 - Standard (default)
473 ** 001 - IrDA (HPSIR)
474 ** 010 - Amplitude Shift Keyed IR @500 KHz
475 ** 011 - Reserved
476 ** 1xx - Reserved
492 ** CR0D - default value 0x03
494 ** Device ID Register - read only
504 ** CR0E - default value 0x02
506 ** Device Revision Register - read only
516 ** CR0F - default value 0x00
521 unsigned test0 : 1; /* Reserved - set to 0 */
522 unsigned test1 : 1; /* Reserved - set to 0 */
523 unsigned test2 : 1; /* Reserved - set to 0 */
524 unsigned test3 : 1; /* Reserved - set t0 0 */
525 unsigned test4 : 1; /* Reserved - set to 0 */
526 unsigned test5 : 1; /* Reserved - set t0 0 */
527 unsigned test6 : 1; /* Reserved - set t0 0 */
528 unsigned test7 : 1; /* Reserved - set to 0 */
533 ** CR10 - default value 0x00
548 ** CR11 - default value 0x00
560 ** CR12 - CR1D are reserved registers
564 ** CR1E - default value 0x80
567 ** 00 - GAMECS disabled
568 ** 01 - 1 byte decode ADR<3:0> = 0001b
569 ** 10 - 8 byte block decode ADR<3:0> = 0XXXb
570 ** 11 - 16 byte block decode ADR<3:0> = XXXXb
582 ** CR1F - default value 0x00
585 ** --- --- ------- ------- ----------
588 ** 2/1.6/1 MB 3.5" (3-mode)
594 ** pins - DRVDEN0 and DRVDEN1.
608 ** CR20 - default value 0x3C
611 ** - To disable this decode set Addr<9:8> = 0
612 ** - A<10> = 0, A<3:0> = 0XXXb to access.
624 ** CR21 - default value 0x3C
627 ** - To disable this decode set Addr<9:8> = 0
628 ** - A<10> = 0, A<3:0> = 0XXXb to access.
640 ** CR22 - default value 0x3D
643 ** - To disable this decode set Addr<9:8> = 0
644 ** - A<10> = 0, A<3:0> = 0110b to access.
656 ** CR23 - default value 0x00
659 ** - To disable this decode set Addr<9:8> = 0
660 ** - A<10> = 0 to access.
661 ** - If EPP is enabled, A<2:0> = XXXb to access.
673 ** CR24 - default value 0x00
676 ** - To disable this decode set Addr<9:8> = 0
677 ** - A<10> = 0, A<2:0> = XXXb to access.
689 ** CR25 - default value 0x00
692 ** - To disable this decode set Addr<9:8> = 0
693 ** - A<10> = 0, A<2:0> = XXXb to access.
705 ** CR26 - default value 0x00
709 ** D3 - D0 DMA
710 ** D7 - D4 Selected
711 ** ------- --------
727 ** CR27 - default value 0x00
731 ** D3 - D0 IRQ
732 ** D7 - D4 Selected
733 ** ------- --------
756 ** CR28 - default value 0x00
760 ** D3 - D0 IRQ
761 ** D7 - D4 Selected
762 ** ------- --------
790 ** CR29 - default value 0x00
794 ** D3 - D0 IRQ
795 ** D7 - D4 Selected
796 ** ------- --------
824 ** this we only define 1 alias here - for CR24 - as the serial
830 ** here - for CR21 - as the IDE address register.
925 * 28-Jan-1997
929 * er 01-May-1997 Fixed pointer conversion errors in
931 * er 28-Jan-1997 Initial version.
933 *--
954 ** function enable/disable scheme.
994 { SMC37c669_DEVICE_IRQ_A, -1 },
995 { SMC37c669_DEVICE_IRQ_B, -1 },
1000 { SMC37c669_DEVICE_IRQ_H, -1 },
1001 { -1, -1 } /* End of table */
1011 { SMC37c669_DEVICE_IRQ_A, -1 },
1012 { SMC37c669_DEVICE_IRQ_B, -1 },
1017 { SMC37c669_DEVICE_IRQ_H, -1 },
1018 { -1, -1 } /* End of table */
1045 { SMC37c669_DEVICE_DRQ_C, -1 },
1046 { -1, -1 } /* End of table */
1115 **--
1156 ** file, it should call a platform-specific external routine at this in SMC37c669_detect()
1219 ** enabled. To avoid replication of code, functions such as
1223 **--
1433 ** Which function to disable
1451 **--
1467 ** Disable the serial 1 IRQ mapping in SMC37c669_disable_device()
1476 ** Disable the serial 1 port base address mapping in SMC37c669_disable_device()
1491 ** Disable the serial 2 IRQ mapping in SMC37c669_disable_device()
1500 ** Disable the serial 2 port base address mapping in SMC37c669_disable_device()
1517 ** Disable the parallel port DMA channel mapping in SMC37c669_disable_device()
1529 ** Disable the parallel port IRQ mapping in SMC37c669_disable_device()
1541 ** Disable the parallel port base address mapping in SMC37c669_disable_device()
1558 ** Disable the floppy controller DMA channel mapping in SMC37c669_disable_device()
1570 ** Disable the floppy controller IRQ mapping in SMC37c669_disable_device()
1582 ** Disable the floppy controller base address mapping in SMC37c669_disable_device()
1597 ** Disable the IDE alternate status base address mapping in SMC37c669_disable_device()
1606 ** Disable the IDE controller base address mapping in SMC37c669_disable_device()
1665 **--
1683 cp->drq = drq; in SMC37c669_configure_device()
1686 cp->irq = irq; in SMC37c669_configure_device()
1689 cp->port1 = port; in SMC37c669_configure_device()
1732 **--
1827 ** copy. Any unused parameters will be set to -1. Any
1831 **--
1846 *drq = cp->drq;
1850 *irq = cp->irq;
1854 *port = cp->port1;
1882 **--
1960 **--
1974 wb( &SMC37c669->index_port, SMC37c669_CONFIG_ON_KEY ); in SMC37c669_config_mode()
1975 wb( &SMC37c669->index_port, SMC37c669_CONFIG_ON_KEY ); in SMC37c669_config_mode()
1979 wb( &SMC37c669->index_port, SMC37c669_CONFIG_OFF_KEY ); in SMC37c669_config_mode()
2004 **--
2009 wb(&SMC37c669->index_port, index); in SMC37c669_read_config()
2010 return rb(&SMC37c669->data_port); in SMC37c669_read_config()
2037 **--
2043 wb( &SMC37c669->index_port, index ); in SMC37c669_write_config()
2044 wb( &SMC37c669->data_port, data ); in SMC37c669_write_config()
2070 **--
2198 **--
2238 ** Returns the translated IRQ, otherwise, returns -1.
2244 **--
2248 int i, translated_irq = -1; in SMC37c669_xlate_irq()
2254 …for ( i = 0; ( SMC37c669_irq_table[i].device_irq != -1 ) || ( SMC37c669_irq_table[i].isa_irq != -1… in SMC37c669_xlate_irq()
2265 …for ( i = 0; ( SMC37c669_irq_table[i].isa_irq != -1 ) || ( SMC37c669_irq_table[i].device_irq != -1… in SMC37c669_xlate_irq()
2290 ** Returns the translated DMA channel, otherwise, returns -1
2296 **--
2300 int i, translated_drq = -1; in SMC37c669_xlate_drq()
2306 …for ( i = 0; ( SMC37c669_drq_table[i].device_drq != -1 ) || ( SMC37c669_drq_table[i].isa_drq != -1… in SMC37c669_xlate_drq()
2317 …for ( i = 0; ( SMC37c669_drq_table[i].isa_drq != -1 ) || ( SMC37c669_drq_table[i].device_drq != -1… in SMC37c669_xlate_drq()
2333 ip->dva = &smc_ddb;
2334 ip->attr = ATTR$M_WRITE | ATTR$M_READ;
2335 ip->len[0] = 0x30;
2336 ip->misc = 0;
2346 ** Allow multiple readers but only one writer. ip->misc keeps track
2349 ip = fp->ip;
2351 if ( fp->mode & ATTR$M_WRITE ) {
2352 if ( ip->misc ) {
2356 ip->misc++;
2361 *fp->offset = xtoi( info );
2371 ip = fp->ip;
2372 if ( fp->mode & ATTR$M_WRITE ) {
2374 ip->misc--;
2390 ip = fp->ip;
2396 if ( !inrange( *fp->offset, 0, ip->len[0] ) )
2398 *buf++ = SMC37c669_read_config( *fp->offset );
2399 *fp->offset += 1;
2415 ip = fp->ip;
2421 if ( !inrange( *fp->offset, 0, ip->len[0] ) )
2423 SMC37c669_write_config( *fp->offset, *buf );
2424 *fp->offset += 1;
2438 printk("-- CR%02x : %02x\n", i, SMC37c669_read_config(i)); in SMC37c669_dump_registers()
2442 * = SMC_init - SMC37c669 Super I/O controller initialization =
2485 -1 in SMC669_Init()
2494 -1 in SMC669_Init()