Documentation/riscv/vector.rst

34       enablement status on execve(). The system-wide default setting can be
49     enablement status of current thread, and the setting at bit[3:2] takes place
50     at next execve(). bit[4] defines the inheritance mode of the setting in
57           but the current enablement status is not off. Setting
62           Vector enablement setting for the calling thread at the next execve()
68           mode for the setting at PR_RISCV_V_VSTATE_CTRL_NEXT_MASK. If the bit
69           is set then the following execve() will not clear the setting in both
71           This setting persists across changes in the system-wide default value.
81         * A valid setting for PR_RISCV_V_VSTATE_CTRL_CUR_MASK takes place
86         * Every successful call overwrites a previous setting for the calling
91     Gets the same Vector enablement status for the calling thread. Setting for
125         setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not
128       * The setting in PR_RISCV_V_VSTATE_CTRL_NEXT_MASK is not