Documentation/riscv/hwprobe.rst

1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Hardware Probing Interface
4 ---------------------------------
6 The RISC-V hardware probing interface is based around a single syscall, which
18 The arguments are split into three groups: an array of key-value pairs, a CPU
19 set, and some flags. The key-value pairs are supplied with a count. Userspace
22 will be cleared to -1, and its value set to 0. The CPU set is defined by
23 CPU_SET(3). For value-like keys (eg. vendor/arch/impl), the returned value will
24 be only be valid if all CPUs in the given set have the same value. Otherwise -1
25 will be returned. For boolean-like keys, the value returned will be a logical
35   as defined by the RISC-V privileged architecture specification.
38   defined by the RISC-V privileged architecture specification.
41   defined by the RISC-V privileged architecture specification.
44   user-visible behavior that this kernel supports.  The following base user ABIs
54       kernel-controlled mechanism such as the vDSO).
62     minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual.
64   * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined
65     by version 2.2 of the RISC-V ISA manual.
67   * :c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by
68     version 1.0 of the RISC-V Vector extension manual.
70   * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is
71        supported, as defined in version 1.0 of the Bit-Manipulation ISA
74   * :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined
75        in version 1.0 of the Bit-Manipulation ISA extensions.
77   * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined
78        in version 1.0 of the Bit-Manipulation ISA extensions.