Documentation/mm/numa.rst

12 or more CPUs, local memory, and/or IO buses.  For brevity and to
17 Each of the 'cells' may be viewed as an SMP [symmetric multi-processor] subset
18 of the system--although some components necessary for a stand-alone SMP system
20 connected together with some sort of system interconnect--e.g., a crossbar or
21 point-to-point link are common types of NUMA system interconnects.  Both of
31 away the cell containing the CPU or IO bus making the memory access is from the
41 [cache misses] to be to "local" memory--memory on the same cell, if any--or
50 CPUs, memory and/or IO buses.  And, again, memory accesses to memory on
51 "closer" nodes--nodes that map to closer cells--will generally experience
63 the existing nodes--or the system memory for non-NUMA platforms--into multiple
66 application features on non-NUMA platforms, and as a sort of memory resource
68 [see Documentation/admin-guide/cgroup-v1/cpusets.rst]
71 subsystem, complete with its own free page lists, in-use page lists, usage
96 "local" to the underlying physical resources and off the system interconnect--
99 NUMA topology of the platform--embodied in the "scheduling domains" data
100 structures [see Documentation/scheduler/sched-domains.rst]--and the scheduler
101 attempts to minimize task migration to distant scheduling domains.  However,
111 Documentation/admin-guide/mm/numa_memory_policy.rst].
113 System administrators can restrict the CPUs and nodes' memories that a non-
115 using control groups and CPUsets.  [see Documentation/admin-guide/cgroup-v1/cpusets.rst]
119 node the "local memory node"--the node of the first zone in CPU's node's
120 zonelist--will not be the node itself.  Rather, it will be the node that the
141 If the architecture supports--does not hide--memoryless nodes, then CPUs