Documentation/mm/mmu_notifier.rst

39  CPU-thread-0  {try to write to addrA}
40  CPU-thread-1  {try to write to addrB}
41  CPU-thread-2  {}
42  CPU-thread-3  {}
43  DEV-thread-0  {read addrA and populate device TLB}
44  DEV-thread-2  {read addrB and populate device TLB}
46  CPU-thread-0  {COW_step0: {mmu_notifier_invalidate_range_start(addrA)}}
47  CPU-thread-1  {COW_step0: {mmu_notifier_invalidate_range_start(addrB)}}
48  CPU-thread-2  {}
49  CPU-thread-3  {}
50  DEV-thread-0  {}
51  DEV-thread-2  {}
53  CPU-thread-0  {COW_step1: {update page table to point to new page for addrA}}
54  CPU-thread-1  {COW_step1: {update page table to point to new page for addrB}}
55  CPU-thread-2  {}
56  CPU-thread-3  {}
57  DEV-thread-0  {}
58  DEV-thread-2  {}
60  CPU-thread-0  {preempted}
61  CPU-thread-1  {preempted}
62  CPU-thread-2  {write to addrA which is a write to new page}
63  CPU-thread-3  {}
64  DEV-thread-0  {}
65  DEV-thread-2  {}
67  CPU-thread-0  {preempted}
68  CPU-thread-1  {preempted}
69  CPU-thread-2  {}
70  CPU-thread-3  {write to addrB which is a write to new page}
71  DEV-thread-0  {}
72  DEV-thread-2  {}
74  CPU-thread-0  {preempted}
75  CPU-thread-1  {COW_step3: {mmu_notifier_invalidate_range_end(addrB)}}
76  CPU-thread-2  {}
77  CPU-thread-3  {}
78  DEV-thread-0  {}
79  DEV-thread-2  {}
81  CPU-thread-0  {preempted}
82  CPU-thread-1  {}
83  CPU-thread-2  {}
84  CPU-thread-3  {}
85  DEV-thread-0  {read addrA from old page}
86  DEV-thread-2  {read addrB from new page}
96 is true even if the thread doing the page table update is preempted right after