Lines Matching refs:B
152 { A == 1; B == 2 }
153 A = 3; x = B;
154 B = 4; y = A;
159 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
160 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
161 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
162 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
163 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
164 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
165 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
166 STORE B=4, ...
186 { A == 1, B == 2, C == 3, P == &A, Q == &C }
187 B = 4; Q = P;
188 P = &B; D = *Q;
195 (Q == &B) and (D == 2)
196 (Q == &B) and (D == 4)
278 X = *A; Y = *B; *D = Z;
282 X = LOAD *A, Y = LOAD *B, STORE *D = Z
283 X = LOAD *A, STORE *D = Z, Y = LOAD *B
284 Y = LOAD *B, X = LOAD *A, STORE *D = Z
285 Y = LOAD *B, STORE *D = Z, X = LOAD *A
286 STORE *D = Z, X = LOAD *A, Y = LOAD *B
287 STORE *D = Z, Y = LOAD *B, X = LOAD *A
577 { A == 1, B == 2, C == 3, P == &A, Q == &C }
578 B = 4;
580 WRITE_ONCE(P, &B);
588 the sequence, Q must be either &A or &B, and that:
591 (Q == &B) implies (D == 4)
593 But! CPU 2's perception of P may be updated _before_ its perception of B, thus
596 (Q == &B) and (D == 2) ????
607 { A == 1, B == 2, C == 3, P == &A, Q == &C }
608 B = 4;
610 WRITE_ONCE(P, &B);
623 variable B might be stored in an even-numbered cache line. Then, if the
625 odd-numbered bank is idle, one can see the new value of the pointer P (&B),
626 but the old value of the variable B (2).
639 { A == 1, B == 2, C = 3, P == &A, Q == &C }
640 B = 4;
642 WRITE_ONCE(P, &B);
650 (Q == &B) && (B == 4)
1004 STORE B = 2
1012 STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
1021 | CPU 1 | : | B=2 | }
1041 { B = 7; X = 9; Y = 8; C = &Y }
1043 STORE B = 2
1045 STORE C = &B LOAD X
1046 STORE D = 4 LOAD C (gets &B)
1047 LOAD *C (reads B)
1054 | |------>| B=2 |----- --->| Y->8 | | of perception on
1060 | | : | C=&B |--- | : : +-------+
1062 | |------>| D=4 | ----------->| C->&B |------>| |
1068 Apparently incorrect ---> | | B->7 |------>| |
1069 perception of B (!) | +-------+ | |
1074 of coherence of B ----->| B->2 | +-------+
1079 In the above example, CPU 2 perceives that B is 7, despite the load of *C
1080 (which would be B) coming after the LOAD of C.
1083 of C and the load of *C (ie: B) on CPU 2:
1087 { B = 7; X = 9; Y = 8; C = &Y }
1089 STORE B = 2
1091 STORE C = &B LOAD X
1092 STORE D = 4 LOAD C (gets &B)
1094 LOAD *C (reads B)
1100 | |------>| B=2 |----- --->| Y->8 |
1106 | | : | C=&B |--- | : : +-------+
1108 | |------>| D=4 | ----------->| C->&B |------>| |
1118 are perceptible to ----->| B->2 |------>| |
1128 { A = 0, B = 9 }
1131 STORE B=2
1132 LOAD B
1142 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1144 | |------>| B=2 |--- | : :
1147 ---------->| B->2 |------>| |
1159 If, however, a read barrier were to be placed between the load of B and the
1164 { A = 0, B = 9 }
1167 STORE B=2
1168 LOAD B
1179 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1181 | |------>| B=2 |--- | : :
1184 ---------->| B->2 |------>| |
1190 prior to the storage of B ---->| A->1 |------>| |
1200 { A = 0, B = 9 }
1203 STORE B=2
1204 LOAD B
1209 Even though the two loads of A both occur after the load of B, they may both
1216 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1218 | |------>| B=2 |--- | : :
1221 ---------->| B->2 |------>| |
1230 prior to the storage of B ---->| A->1 |------>| 2nd |
1242 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1244 | |------>| B=2 |--- | : :
1247 ---------->| B->2 |------>| |
1262 load of B came up with B == 2. No such guarantee exists for the first load of
1284 LOAD B
1293 --->| B->2 |------>| |
1312 LOAD B
1324 --->| B->2 |------>| |
1346 --->| B->2 |------>| |
1395 on CPU B follows a load from the same variable executing on CPU A (and
1397 multicopy-atomic systems, CPU B's load must return either the same value
2045 *B = b;
2049 ACQUIRE M, STORE *B, STORE *A, RELEASE M
2065 *B = b;
2069 ACQUIRE N, STORE *B, STORE *A, RELEASE M
2109 *B = b;
2119 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
2125 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
2126 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
2127 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
2128 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
2320 WRITE_ONCE(*B, b); WRITE_ONCE(*F, f);
2329 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
2333 *B, *C or *D preceding ACQUIRE M
2334 *A, *B or *C following RELEASE M
2792 WRITE_ONCE(*B, b);
2801 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2833 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B