Documentation/gpu/tegra.rst

2  drm/tegra NVIDIA Tegra GPU and display driver
5 NVIDIA Tegra SoCs support a set of display, graphics and video functions via
6 the host1x controller. host1x supplies command streams, gathered from a push
11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18   - A host1x driver that provides infrastructure and access to the host1x
21   - A KMS driver that supports the display controllers as well as a number of
24   - A set of custom userspace IOCTLs that can be used to submit jobs to the
30 The various host1x clients need to be bound together into a logical device in
32 this is implemented in the host1x driver. When a driver is registered with the
33 infrastructure it provides a list of compatible strings specifying the devices
34 that it needs. The infrastructure creates a logical device and scan the device
35 tree for matching device nodes, adding the required clients to a list. Drivers
40 device using a driver-provided function which will set up the bits specific to
48 -------------------------------
50 .. kernel-doc:: include/linux/host1x.h
52 .. kernel-doc:: drivers/gpu/host1x/bus.c
56 --------------------------
58 .. kernel-doc:: drivers/gpu/host1x/syncpt.c
64 The display hardware has remained mostly backwards compatible over the various
66 make it difficult to support with a parameterized driver.
68 Display Controllers
69 -------------------
71 Tegra SoCs have two display controllers, each of which can be associated with
72 zero or more outputs. Outputs can also share a single display controller, but
73 only if they run with compatible display timings. Two display controllers can
74 also share a single framebuffer, allowing cloned configurations even if modes
75 on two outputs don't match. A display controller is modelled as a CRTC in KMS
78 On Tegra186, the number of display controllers has been increased to three. A
79 display controller can no longer drive all of the outputs. While two of these
86 A display controller controls a set of windows that can be used to composite
90 assume a fixed Z ordering of the windows (window A is the root window, that
91 is, the lowest, while windows B and C are overlaid on top of window A). The
94 content. In KMS, each window is modelled as a plane. Each display controller
95 has a hardware cursor that is exposed as a cursor plane.
98 -------
102 very simple RGB interfaces (one per display controller), recent generations no
105 Outputs are modelled as a composite encoder/connector pair.
131 eDP was first introduced in Tegra124 where it was used to drive the display
143 -----------
145 The ``DRM_IOCTL_TEGRA_GEM_CREATE`` IOCTL is used to create a GEM buffer object
146 with Tegra-specific flags. This is useful for buffers that should be tiled, or
149 After a GEM buffer object has been created, its memory can be mapped by an
154 ----------
156 The current value of a syncpoint can be obtained by executing the
160 Userspace can also request blocking on a syncpoint. To do so, it needs to
163 syncpoint reaches that value or after a specified timeout.
166 -------------------------
168 Before an application can submit command streams to host1x it needs to open a
170 IDs are used to identify the target of the channel. When a channel is no
172 IOCTL. To retrieve the syncpoint associated with a channel, an application
175 After opening a channel, submitting command streams is easy. The application
176 writes commands into the memory backing a GEM buffer object and passes these