amdgpu/display/dcn-overview.rst

2 Display Core Next (DCN)
5 To equip our readers with the basic knowledge of how AMD Display Core Next
7 you can see a picture that provides a DCN overview, keep in mind that this is a
10 .. kernel-figure:: dc_pipeline_overview.svg
15 * **Display Controller Hub (DCHUB)**: This is the gateway between the Scalable
19 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
24   multiple planes, using global or per-pixel alpha.
27   the display.
32 * **Display Output (DIO)**: Codify the output to the display connected to our
35 * **Display Writeback (DWB)**: It provides the ability to write the output of
36   the display pipe back to memory as video frames.
38 * **Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB
43   the Display Micro-Controller Unit - version B (DMCUB), which is handled via
47   for all of the display controller clock domains.
52 every ASIC has variations around this base model. Notice that the display
54 the SDP as the element from our Data Fabric that feeds the display pipe.
59 want to drive an 8k@60Hz with a DSC enabled, our DCN may require 4 DPP and 2
61 specific scenario. Orchestrate all of these components together requires a
67 2. Global sync signals (green): It is a set of synchronization signals composed
76 All of these components are represented by a data structure named dc_state.
77 From DCHUB to MPC, we have a representation called dc_plane; from MPC to OPTC,
79 that HUBP accesses a surface using a specific format read from memory, and our
81 be sent to the display via dc_stream and dc_link.
84 ----------------------
86 Display pipeline can be broken down into two components that are usually
89 * DCHUB (Mainly referring to a subcomponent named HUBP)
99 OPP and OPTC are two joining blocks between FE and BE. On a side note, this is
100 a one-to-one mapping of the link encoder to PHY, but we can configure the DCN
102 is to change, blend and compose pixel data, while BE's job is to frame a
103 generic pixel stream to a specific display's pixel stream.
106 ---------
114 representation and convert them to a DCN specific floating-point format (i.e.,
115 different from the IEEE floating-point format). In the process, CNVC also
116 applies a degamma function to transform the data from non-linear to linear
117 space to relax the floating-point calculations following. Data would stay in
118 this floating-point format from DPP to OPP.
123 depth format), bit-depth reduction/dithering would kick in. In OPP, we would
124 also apply a regamma function to introduce the gamma removed earlier back.
128 ---------------------
133 pipeline** or **pipeline** or just **pipe** as an abstraction to indicate a
135 core treats DCN blocks as individual resources, meaning we can build a pipeline
137 In actuality, we can't connect an arbitrary block from one pipe to a block from
142 .. kernel-figure:: pipeline_4k_no_split.svg
144 Additionally, let's take a look at parts of the DTN log (see
145 'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since
146 this log can help us to see part of this pipeline behavior in real-time::
160 we have just a single **pipeline** where the data flows from DCHUB to DIO, as
164 .. kernel-figure:: pipeline_4k_split.svg
178 From the above example, we now split the display pipeline into two vertical
179 parts of 1920x2160 (i.e., 3440x2160), and as a result, we could reduce the
182 that the pipe configuration can vary a lot according to the display
187 -----------
194 in order to support outputs that need a very high pixel clock, or for
203 calculated by the Display Mode Library - DML (drivers/gpu/drm/amd/display/dc/dml)
204 based on a large number of parameters and ensure our hardware is able to feed
215 Since DCN hardware is double-buffered the DC driver is able to program the
220 .. kernel-figure:: global_sync_vblank.svg
223 to a number of negative consequences, most of them quite catastrophic.
225 The following picture shows how global sync allows for a mailbox style of
226 updates, i.e. it allows for multiple re-configurations between VUpdate
230 .. kernel-figure:: config_example.svg