Documentation/fpga/dfl.rst

216 (/sys/class/fpga_region/regionX/dfl-fme.n/):
288 (/sys/class/fpga_region/<regionX>/<dfl-port.m>/):
470 the sysfs hierarchy under /sys/class/fpga_region.
475 FPGA regions are created under /sys/class/fpga_region/::
477 	/sys/class/fpga_region/region0
478 	/sys/class/fpga_region/region1
479 	/sys/class/fpga_region/region2
488 	/sys/class/fpga_region/region0/dfl-fme.0
489 	/sys/class/fpga_region/region0/dfl-port.0
490 	/sys/class/fpga_region/region0/dfl-port.1
493 	/sys/class/fpga_region/region3/dfl-fme.1
494 	/sys/class/fpga_region/region3/dfl-port.2
495 	/sys/class/fpga_region/region3/dfl-port.3
500 	/sys/class/fpga_region/<regionX>/<dfl-fme.n>/
501 	/sys/class/fpga_region/<regionX>/<dfl-port.m>/
508 	/sys/class/fpga_region/<regionX>/<dfl-fme.n>/dev
509 	/sys/class/fpga_region/<regionX>/<dfl-port.n>/dev