Documentation/fpga/dfl.rst

85     |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 REV 12|11 ID 0| 0x00
94   * Type - The type of DFH (e.g. FME, AFU, or private feature).
95   * DFH VER - The version of the DFH.
97   * EOL - Set if the DFH is the end of the Device Feature List (DFL).
98   * Next - The offset in bytes of the next DFH in the DFL from the DFH start,
99     and the start of a DFH must be aligned to an 8 byte boundary.
122 * Decouples the DFH location from the register space of the feature itself.
125 The format of Version 1 of the Device Feature Header (DFH) is shown below::
128     |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 REV 12|11 ID 0| 0x00
153   * Type - The type of DFH (e.g. FME, AFU, or private feature).
154   * DFH VER - The version of the DFH.
156   * EOL - Set if the DFH is the end of the Device Feature List (DFL).
157   * Next - The offset in bytes of the next DFH in the DFL from the DFH start,
158     and the start of a DFH must be aligned to an 8 byte boundary.
175     the value is the offset from the start of the DFH of the feature's registers.
180   * Params - Set if DFH has a list of parameter blocks.