Lines Matching refs:GPU
116 Several stacks of HBM chips connect to the CPU or GPU through an ultra-fast
196 GPU nodes can be accessed the same way as the data fabric on CPU nodes.
199 and each GPU data fabric contains four Unified Memory Controllers (UMC).
207 Memory controllers on AMD GPU nodes can be represented in EDAC thusly:
209 GPU DF / GPU Node -> EDAC MC
210 GPU UMC -> EDAC CSROW
211 GPU UMC channel -> EDAC CHANNEL
218 - The CPU UMC (Unified Memory Controller) is mostly the same as the GPU UMC.
224 - GPU UMCs use 1 chip select, So UMC = EDAC CSROW.
225 - GPU UMCs use 8 channels, So UMC channel = EDAC channel.
230 AMD GPU nodes are enumerated in sequential order based on the PCI
231 hierarchy, and the first GPU node is assumed to have a Node ID value
237 mc2 |- GPU card[0] => node 0(mc1), node 1(mc2)
239 mc4 |- GPU card[1] => node 0(mc3), node 1(mc4)
241 mc6 |- GPU card[2] => node 0(mc5), node 1(mc6)
243 mc8 |- GPU card[3] => node 0(mc7), node 1(mc8)
254 GPU Nodes are enumerated sequentially after CPU nodes have been populated
255 GPU card 1 # Each MI200 GPU has 2 nodes/mcs
256 ├── mc 1 # GPU node 0 == mc1, Each MC node has 4 UMCs/CSROWs
279 ├── mc 2 # GPU node 1 == mc2
280 │ ├── .. # each GPU has total 64 GB
282 GPU card 2
288 GPU card 3
294 GPU card 4