Lines Matching refs:memory

18 The individual DRAM chips on a memory stick.  These devices commonly
20 provides the number of bits that the memory controller expects:
25 A printed circuit board that aggregates multiple memory devices in
32 A physical connector on the motherboard that accepts a single memory
37 A memory controller channel, responsible to communicate with a group of
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
48 just one memory stick when an error occurs, as the error correction code
54 The data accessed by the memory controller is contained into one dimm
62 The data size accessed by the memory controller is interlaced into two
71 dual channel 128 bits. It may not be visible by the memory controller,
72 as some DIMM types have a memory buffer that can hide direct access to
77 A Single-ranked stick has 1 chip-select row of memory. Motherboards
78 commonly drive two chip-select pins to a memory stick. A single-ranked
86 sets of memory devices.  The two rows cannot be accessed concurrently.
93 of memory devices. The two rows cannot be accessed concurrently.
94 "Double-sided" is irrespective of the memory devices being mounted on
95 both sides of the memory stick.
99 All of the memory sticks that are required for a single memory access or
100 all of the memory sticks spanned by a chip-select row.  A single socket
111 HBM is a new memory type with low power consumption and ultra-wide
112 communication lanes. It uses vertically stacked memory chips (DRAM dies)
125 to describe the memory controllers, with is an opaque struct for the EDAC
152 …s the APIs for the same, provide for registering EDAC type devices which are NOT standard memory or
173 	mc/		<existing memory device directory>
222   marketing speak. CPU has X memory channels, etc.