Documentation/driver-api/edac.rst

5 ----------------------------------------
7 There are several things to be aware of that aren't at all obvious, like
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
21 typically 72 bits, in order to provide 64 bits + 8 bits of ECC data.
37 A memory controller channel, responsible to communicate with a group of
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
47 some performance penalty. Also, it is generally not possible to point to
49 is calculated using two DIMMs instead of one. Due to that, it is capable
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
64 bits with ECC), the data flows to the CPU using a 128 bits parallel
67 * Chip-select row
69 This is the name of the DRAM signal used to select the DRAM ranks to be
70 accessed. Common chip-select rows for single channel are 64 bits, for
72 as some DIMM types have a memory buffer that can hide direct access to
75 * Single-Ranked stick
77 A Single-ranked stick has 1 chip-select row of memory. Motherboards
78 commonly drive two chip-select pins to a memory stick. A single-ranked
83 * Double-Ranked stick
85 A double-ranked stick has two chip-select rows which access different
88 * Double-sided stick
90 **DEPRECATED TERM**, see :ref:`Double-Ranked stick <doubleranked>`.
92 A double-sided stick has two chip-select rows which access different sets
94 "Double-sided" is irrespective of the memory devices being mounted on
100 all of the memory sticks spanned by a chip-select row.  A single socket
101 set has two chip-select rows and if double-sided sticks are used these
102 will occupy those chip-select rows.
106 This term is avoided because it is unclear when needing to distinguish
107 between chip-select rows and socket sets.
111 HBM is a new memory type with low power consumption and ultra-wide
113 interconnected by microscopic wires called "through-silicon vias," or
116 Several stacks of HBM chips connect to the CPU or GPU through an ultra-fast
118 are nearly indistinguishable from on-chip integrated RAM.
121 ------------------
125 to describe the memory controllers, with is an opaque struct for the EDAC
126 drivers. Only the EDAC core is allowed to touch it.
128 .. kernel-doc:: include/linux/edac.h
130 .. kernel-doc:: drivers/edac/edac_mc.h
132 PCI Controllers
133 ---------------
135 The EDAC subsystem provides a mechanism to handle PCI controllers by calling
137 :c:type:`edac_pci_ctl_info` to describe the PCI controllers.
139 .. kernel-doc:: drivers/edac/edac_pci.h
142 -----------
144 The EDAC subsystem also provides a generic mechanism to report errors on
153 PCI, like:
155 - CPU caches (L1 and L2)
156 - DMA engines
157 - Core CPU switches
158 - Fabric switch units
159 - PCIe interface controllers
160 - other EDAC/ECC type devices that can be monitored for
166 Each CPU core would have its own L1 cache, while sharing L2 and maybe L3
172 	pci/		<existing pci directory (if available)>
174 	cpu/cpu0/..	<L1 and L2 block directory>
175 		/L1-cache/ce_count
177 		/L2-cache/ce_count
179 	cpu/cpu1/..	<L1 and L2 block directory>
180 		/L1-cache/ce_count
182 		/L2-cache/ce_count
188 .. kernel-doc:: drivers/edac/edac_device.h
192 ----------------------------
196 GPU nodes can be accessed the same way as the data fabric on CPU nodes.
200 Each UMC contains eight channels. Each UMC channel controls one 128-bit
201 HBM2e (2GB) channel (equivalent to 8 X 2GB ranks).  This creates a total
202 of 4096-bits of DRAM data bus.
209 	GPU DF / GPU Node -> EDAC MC
210 	GPU UMC           -> EDAC CSROW
211 	GPU UMC channel   -> EDAC CHANNEL
213 For example: a heterogeneous system with 1 AMD CPU is connected to
218 - The CPU UMC (Unified Memory Controller) is mostly the same as the GPU UMC.
221 - CPU UMCs use 1 channel, In this case UMC = EDAC channel. This follows the
222   marketing speak. CPU has X memory channels, etc.
223 - CPU UMCs use up to 4 chip selects, So UMC chip select = EDAC CSROW.
224 - GPU UMCs use 1 chip select, So UMC = EDAC CSROW.
225 - GPU UMCs use 8 channels, So UMC channel = EDAC channel.
227 The EDAC subsystem provides a mechanism to handle AMD heterogeneous
230 AMD GPU nodes are enumerated in sequential order based on the PCI
231 hierarchy, and the first GPU node is assumed to have a Node ID value
232 following those of the CPU nodes after latter are fully populated::
235 		mc0   - CPU MC node 0
237 		mc2  |- GPU card[0] => node 0(mc1), node 1(mc2)
239 		mc4  |- GPU card[1] => node 0(mc3), node 1(mc4)
241 		mc6  |- GPU card[2] => node 0(mc5), node 1(mc6)
243 		mc8  |- GPU card[3] => node 0(mc7), node 1(mc8)
245 For example, a heterogeneous system with one AMD CPU is connected to
251 	CPU			# CPU node
254 	GPU Nodes are enumerated sequentially after CPU nodes have been populated