bindings/x86/ce4100.txt

2 ---------------------------
5 format: <vendor>,<chip>-<device>.
10 The CPU nodes
11 -------------
14 		#address-cells = <1>;
15 		#size-cells = <0>;
17 		cpu@0 {
18 			device_type = "cpu";
23 		cpu@2 {
24 			device_type = "cpu";
30 A "cpu" node describes one logical processor (hardware thread).
34 - device_type
35 	Device type, must be "cpu".
37 - reg
38 	Local APIC ID, the unique number assigned to each processor by
42 ------------
44 This node describes the in-core peripherals. Required property:
45   compatible = "intel,ce4100-cp";
47 The PCI node
48 ------------
49 This node describes the PCI bus on the SoC. Its property should be
50   compatible = "intel,ce4100-pci", "pci";
52 If the OS is using the IO-APIC for interrupt routing then the reported
53 interrupt numbers for devices is no longer true. In order to obtain the
55 to contain the interrupt property. Besides the interrupt property it has
56 to contain at least the reg property containing the PCI bus address and
57 compatible property according to "PCI Bus Binding Revision 2.1".