bindings/usb/ti%2Cj721e-usb.yaml

1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,j721e-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI wrapper module for the Cadence USBSS-DRD controller
10   - Roger Quadros <rogerq@kernel.org>
15       - const: ti,j721e-usb
16       - const: ti,am64-usb
17       - items:
18           - const: ti,j721e-usb
19           - const: ti,am64-usb
26   power-domains:
30       Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
38   clock-names:
40       - const: ref
41       - const: lpm
43   ti,usb2-only:
50   ti,vbus-divider:
52       Should be present if USB VBUS line is connected to the
53       VBUS pin of the SoC via a 1/3 voltage divider.
56   '#address-cells':
59   '#size-cells':
62   dma-coherent: true
69   - compatible
70   - reg
71   - power-domains
72   - clocks
73   - clock-names
78   - |
79     #include <dt-bindings/soc/ti,sci_pm_domain.h>
80     #include <dt-bindings/interrupt-controller/arm-gic.h>
83         #address-cells = <2>;
84         #size-cells = <2>;
87             compatible = "ti,j721e-usb";
89             power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
91             clock-names = "ref", "lpm";
92             assigned-clocks = <&k3_clks 288 15>;	/* USB2_REFCLK */
93             assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
94             #address-cells = <2>;
95             #size-cells = <2>;
102                   reg-names = "otg", "xhci", "dev";
106                   interrupt-names = "host",
109                   maximum-speed = "super-speed";