Lines Matching +full:gcc +full:- +full:msm8998
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Andy Gross <agross@kernel.org>
13 # Select only our matches, not all jedec,ufs-2.0
20 - compatible
25 - enum:
26 - qcom,msm8994-ufshc
27 - qcom,msm8996-ufshc
28 - qcom,msm8998-ufshc
29 - qcom,sa8775p-ufshc
30 - qcom,sc8280xp-ufshc
31 - qcom,sdm845-ufshc
32 - qcom,sm6115-ufshc
33 - qcom,sm6350-ufshc
34 - qcom,sm8150-ufshc
35 - qcom,sm8250-ufshc
36 - qcom,sm8350-ufshc
37 - qcom,sm8450-ufshc
38 - qcom,sm8550-ufshc
39 - const: qcom,ufshc
40 - const: jedec,ufs-2.0
46 clock-names:
50 dma-coherent: true
56 interconnect-names:
58 - const: ufs-ddr
59 - const: cpu-ufs
68 phy-names:
70 - const: ufsphy
72 power-domains:
83 reg-names:
85 - const: std
86 - const: ice
88 required-opps:
94 '#reset-cells':
97 reset-names:
99 - const: rst
101 reset-gpios:
107 - compatible
108 - reg
111 - $ref: ufs-common.yaml
113 - if:
118 - qcom,msm8998-ufshc
119 - qcom,sa8775p-ufshc
120 - qcom,sc8280xp-ufshc
121 - qcom,sm8250-ufshc
122 - qcom,sm8350-ufshc
123 - qcom,sm8450-ufshc
124 - qcom,sm8550-ufshc
130 clock-names:
132 - const: core_clk
133 - const: bus_aggr_clk
134 - const: iface_clk
135 - const: core_clk_unipro
136 - const: ref_clk
137 - const: tx_lane0_sync_clk
138 - const: rx_lane0_sync_clk
139 - const: rx_lane1_sync_clk
143 reg-names:
146 - if:
151 - qcom,sdm845-ufshc
152 - qcom,sm6350-ufshc
153 - qcom,sm8150-ufshc
159 clock-names:
161 - const: core_clk
162 - const: bus_aggr_clk
163 - const: iface_clk
164 - const: core_clk_unipro
165 - const: ref_clk
166 - const: tx_lane0_sync_clk
167 - const: rx_lane0_sync_clk
168 - const: rx_lane1_sync_clk
169 - const: ice_core_clk
173 reg-names:
176 - reg-names
178 - if:
183 - qcom,msm8996-ufshc
189 clock-names:
191 - const: core_clk_src
192 - const: core_clk
193 - const: bus_clk
194 - const: bus_aggr_clk
195 - const: iface_clk
196 - const: core_clk_unipro_src
197 - const: core_clk_unipro
198 - const: core_clk_ice
199 - const: ref_clk
200 - const: tx_lane0_sync_clk
201 - const: rx_lane0_sync_clk
205 reg-names:
208 - if:
213 - qcom,sm6115-ufshc
219 clock-names:
221 - const: core_clk
222 - const: bus_aggr_clk
223 - const: iface_clk
224 - const: core_clk_unipro
225 - const: ref_clk
226 - const: tx_lane0_sync_clk
227 - const: rx_lane0_sync_clk
228 - const: ice_core_clk
232 reg-names:
235 - reg-names
237 # TODO: define clock bindings for qcom,msm8994-ufshc
239 - if:
241 - qcom,ice
261 - |
262 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
263 #include <dt-bindings/clock/qcom,rpmh.h>
264 #include <dt-bindings/gpio/gpio.h>
265 #include <dt-bindings/interconnect/qcom,sm8450.h>
266 #include <dt-bindings/interrupt-controller/arm-gic.h>
269 #address-cells = <2>;
270 #size-cells = <2>;
273 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
274 "jedec,ufs-2.0";
278 phy-names = "ufsphy";
279 lanes-per-direction = <2>;
280 #reset-cells = <1>;
281 resets = <&gcc GCC_UFS_PHY_BCR>;
282 reset-names = "rst";
283 reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
285 vcc-supply = <&vreg_l7b_2p5>;
286 vcc-max-microamp = <1100000>;
287 vccq-supply = <&vreg_l9b_1p2>;
288 vccq-max-microamp = <1200000>;
290 power-domains = <&gcc UFS_PHY_GDSC>;
294 interconnect-names = "ufs-ddr", "cpu-ufs";
296 clock-names = "core_clk",
304 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
305 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
306 <&gcc GCC_UFS_PHY_AHB_CLK>,
307 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
309 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
310 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
311 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
312 freq-table-hz = <75000000 300000000>,