Lines Matching full:mtu1

18       for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
35     - [MTU1, MTU2]
38           of MTU1 and MTU2 (when TMDR3.LWA = 1)
56     - [MTU0/MTU5, MTU1, MTU2, and MTU8]
57         - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
76     MTU1 and MTU2 operate independently, and cascade connection 32-bit phase
77     counting mode in which MTU1 and MTU2 are cascaded.
83       count0 - MTU1 16-bit phase counting
85       count2 - MTU1+ MTU2 32-bit phase counting
97       pwm2  - MTU1.MTIOC1A PWM mode 1
128       - description: MTU1.TGRA input capture/compare match
129       - description: MTU1.TGRB input capture/compare match
130       - description: MTU1.TCNT overflow
131       - description: MTU1.TCNT underflow