Lines Matching full:hardware

17   framework for its hardware implementation is alike to SPI bus and its timing
21   48 hardware channels to access analog chip. For 2 software read/write channels,
22   users should set ADI registers to access analog chip. For hardware channels,
23   we can configure them to allow other hardware components to use it independently,
24   which means we can just link one analog chip address to one hardware channel,
25   then users can access the mapped analog chip address by this hardware channel
26   triggered by hardware components instead of ADI software channels.
28   Thus we introduce one property named "sprd,hw-channels" to configure hardware
29   channels, the first value specifies the hardware channel id which is used to
30   transfer data triggered by hardware automatically, and the second value specifies
31   the analog chip address where user want to access by hardware components.
35   one hardware spinlock protection to prevent other systems from reading/writing
38   Then we need one hardware spinlock to synchronize between the multiple subsystems.
41   subsystem accessing, that means no need to add hardware spinlock to synchronize,
42   thus change the hardware spinlock support to be optional to keep backward
66     description: A list of hardware channels
71         - description: The hardware channel id which is used to transfer data
72             triggered by hardware automatically, channel id 0-1 are for software
73             use, 2-49 are hardware channels.
77             hardware components.