bindings/riscv/cpus.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10   - Paul Walmsley <paul.walmsley@sifive.com>
11   - Palmer Dabbelt <palmer@sifive.com>
12   - Conor Dooley <conor@kernel.org>
15   This document uses some terminology common to the RISC-V community
19   mandated by the RISC-V ISA: a PC and some registers.  This
27   - $ref: /schemas/cpu.yaml#
28   - $ref: extensions.yaml
33       - items:
34           - enum:
35               - andestech,ax45mp
36               - canaan,k210
37               - sifive,bullet0
38               - sifive,e5
39               - sifive,e7
40               - sifive,e71
41               - sifive,rocket0
42               - sifive,s7
43               - sifive,u5
44               - sifive,u54
45               - sifive,u7
46               - sifive,u74
47               - sifive,u74-mc
48               - thead,c906
49               - thead,c910
50           - const: riscv
51       - items:
52           - enum:
53               - sifive,e51
54               - sifive,u54-mc
55           - const: sifive,rocket0
56           - const: riscv
57       - const: riscv    # Simulator only
59       Identifies that the hart uses the RISC-V instruction set
62   mmu-type:
65       hart.  These values originate from the RISC-V Privileged
70       - riscv,sv32
71       - riscv,sv39
72       - riscv,sv48
73       - riscv,sv57
74       - riscv,none
76   riscv,cbom-block-size:
81   riscv,cboz-block-size:
86   # RISC-V has multiple properties for cache op block sizes as the sizes
88   cache-op-block-size: false
89   # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
90   timebase-frequency: false
92   interrupt-controller:
98       '#interrupt-cells':
102         const: riscv,cpu-intc
104       interrupt-controller: true
107       - '#interrupt-cells'
108       - compatible
109       - interrupt-controller
111   cpu-idle-states:
112     $ref: /schemas/types.yaml#/definitions/phandle-array
117       by this hart (see ./idle-states.yaml).
119   capacity-dmips-mhz:
121       u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
122       DMIPS/MHz, relative to highest capacity-dmips-mhz
126   - required:
127       - riscv,isa
128   - required:
129       - riscv,isa-base
132   riscv,isa-base: [ "riscv,isa-extensions" ]
133   riscv,isa-extensions: [ "riscv,isa-base" ]
136   - interrupt-controller
141   - |
144         #address-cells = <1>;
145         #size-cells = <0>;
146         timebase-frequency = <1000000>;
148                 clock-frequency = <0>;
151                 i-cache-block-size = <64>;
152                 i-cache-sets = <128>;
153                 i-cache-size = <16384>;
155                 riscv,isa-base = "rv64i";
156                 riscv,isa-extensions = "i", "m", "a", "c";
158                 cpu_intc0: interrupt-controller {
159                         #interrupt-cells = <1>;
160                         compatible = "riscv,cpu-intc";
161                         interrupt-controller;
165                 clock-frequency = <0>;
167                 d-cache-block-size = <64>;
168                 d-cache-sets = <64>;
169                 d-cache-size = <32768>;
170                 d-tlb-sets = <1>;
171                 d-tlb-size = <32>;
173                 i-cache-block-size = <64>;
174                 i-cache-sets = <64>;
175                 i-cache-size = <32768>;
176                 i-tlb-sets = <1>;
177                 i-tlb-size = <32>;
178                 mmu-type = "riscv,sv39";
180                 tlb-split;
181                 riscv,isa-base = "rv64i";
182                 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
184                 cpu_intc1: interrupt-controller {
185                         #interrupt-cells = <1>;
186                         compatible = "riscv,cpu-intc";
187                         interrupt-controller;
192   - |
195         #address-cells = <1>;
196         #size-cells = <0>;
201                 mmu-type = "riscv,sv48";
202                 riscv,isa-base = "rv64i";
203                 riscv,isa-extensions = "i", "m", "a", "f", "d", "c";
205                 interrupt-controller {
206                         #interrupt-cells = <1>;
207                         interrupt-controller;
208                         compatible = "riscv,cpu-intc";