bindings/pinctrl/qcom%2Csm8450-tlmm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Vinod Koul <vkoul@kernel.org>
16   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20     const: qcom,sm8450-tlmm
28   interrupt-controller: true
29   "#interrupt-cells": true
30   gpio-controller: true
32   gpio-reserved-ranges:
36   gpio-line-names:
39   "#gpio-cells": true
40   gpio-ranges: true
41   wakeup-parent: true
44   - compatible
45   - reg
50   "-state$":
52       - $ref: "#/$defs/qcom-sm8450-tlmm-state"
53       - patternProperties:
54           "-pins$":
55             $ref: "#/$defs/qcom-sm8450-tlmm-state"
59   qcom-sm8450-tlmm-state:
62       Pinctrl node's client devices use subnodes for desired pin configuration.
63       Client device subnodes use below standard properties.
64     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
74             - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
75             - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
108       - pins
111   - |
112     #include <dt-bindings/interrupt-controller/arm-gic.h>
114         compatible = "qcom,sm8450-tlmm";
116         gpio-controller;
117         #gpio-cells = <2>;
118         gpio-ranges = <&tlmm 0 0 211>;
119         interrupt-controller;
120         #interrupt-cells = <2>;
123         gpio-wo-state {
128         uart-w-state {
129             rx-pins {
132                 bias-pull-up;
135             tx-pins {
138                 bias-disable;